at28c010.vhd

vhdl cod for ram.For sp3e

            SetupLow        => tsetup_WENeg_CENeg,
            CheckEnabled    => true,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_WENeg_CENeg_setup,
            Violation       => Tviol_WENeg_CENeg_setup
        );

        -- Hold Check between WE# and CE# /
        VitalSetupHoldCheck (
            TestSignal      => WENeg_ipd,
            TestSignalName  => "WE#",
            RefSignal       => CENeg_ipd,
            RefSignalName   => "CE#",
            HoldLow         => thold_WENeg_CENeg,
            CheckEnabled    => true,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_WENeg_CENeg_hold,
            Violation       => Tviol_WENeg_CENeg_hold
        );

        -- Setup/Hold Check between IO0 and CE# \
        VitalSetupHoldCheck (
            TestSignal      => IO0_ipd,
            TestSignalName  => "IO0",
            RefSignal       => CENeg_ipd,
            RefSignalName   => "CE#",
            SetupHigh       => tsetup_IO0_CENeg,
            SetupLow        => tsetup_IO0_CENeg,
            HoldHigh        => thold_IO0_CENeg,
            HoldLow         => thold_IO0_CENeg,
            CheckEnabled    => true,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_IO0_CENeg,
            Violation       => Tviol_IO0_CENeg
        );

        -- Setup Check between IO0 and WE#
        VitalSetupHoldCheck (
            TestSignal      => IO0_ipd,
            TestSignalName  => "IO0",
            RefSignal       => WENeg_ipd,
            RefSignalName   => "WE#",
            SetupHigh       => tsetup_IO0_WENeg,
            SetupLow        => tsetup_IO0_WENeg,
            HoldHigh        => thold_IO0_WENeg,
            HoldLow         => thold_IO0_WENeg,
            CheckEnabled    => true,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_IO0_WENeg,
            Violation       => Tviol_IO0_WENeg
        );

        -- Setup/Hold Check between IO0 and WE#
        VitalSetupHoldCheck (
            TestSignal      => IO0_ipd,
            TestSignalName  => "IO0",
            RefSignal       => WENeg_ipd,
            RefSignalName   => "WE#",
            HoldHigh        => thold_IO0_WENeg_Write_noedge_posedge,
            HoldLow         => thold_IO0_WENeg_Write_noedge_posedge,
            CheckEnabled    => write = '1' AND NOT rising_edge(read),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_IO0_WENeg_Write,
            Violation       => Tviol_IO0_WENeg_Write
        );

        -- Hold Check between IO0 and WE#
        VitalSetupHoldCheck (
            TestSignal      => IO0_ipd,
            TestSignalName  => "IO0",
            RefSignal       => WENeg_ipd,
            RefSignalName   => "WE#",
            HoldHigh        => thold_IO0_WENeg_DataPolling_noedge_posedge,
            HoldLow         => thold_IO0_WENeg_DataPolling_noedge_posedge,
            CheckEnabled    => rising_edge(read) AND write = '1',
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_IO0_WENeg_DataPolling,
            Violation       => Tviol_IO0_WENeg_DataPolling
        );

        -- Hold Check between OE# and CE#
        VitalSetupHoldCheck (
            TestSignal      => OENeg_ipd,
            TestSignalName  => "OE#",
            RefSignal       => WENeg_ipd,
            RefSignalName   => "CE#",
            HoldHigh        => thold_OENeg_CENeg,
            CheckEnabled    => true,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_OENeg_CENeg,
            Violation       => Tviol_OENeg_CENeg
        );

        -- Period Check CE#
        VitalPeriodPulseCheck (
            TestSignal      =>  CENeg_ipd,
            TestSignalName  =>  "CE#",
            PulseWidthLow   =>  tpw_CENeg_negedge,
            PeriodData      =>  PD_CENeg,
            XOn             =>  XOn,
            MsgOn           =>  MsgOn,
            Violation       =>  Pviol_CENeg,
            HeaderMsg       =>  InstancePath & PartID,
            CheckEnabled    =>  true );

        -- Period Check WE#
        VitalPeriodPulseCheck (
            TestSignal      =>  WENeg_ipd,
            TestSignalName  =>  "WE#",
            PulseWidthHigh  =>  tpw_WENeg_posedge,
            PulseWidthLow   =>  tpw_WENeg_negedge,
            PeriodData      =>  PD_WENeg,
            XOn             =>  XOn,
            MsgOn           =>  MsgOn,
            Violation       =>  Pviol_WENeg,
            HeaderMsg       =>  InstancePath & PartID,
            CheckEnabled    =>  true );

         -- Period Check OE#
        VitalPeriodPulseCheck (
            TestSignal      =>  OENeg_ipd,
            TestSignalName  =>  "OE#",
            PulseWidthHigh  =>  tpw_OENeg_DataPolling_posedge,
            PeriodData      =>  PD_OENeg,
            XOn             =>  XOn,
            MsgOn           =>  MsgOn,
            Violation       =>  Pviol_OENeg,
            HeaderMsg       =>  InstancePath & PartID,
            CheckEnabled    =>  rising_edge(read) AND write = '1');

        Violation := Tviol_A0_WENeg                 OR
                     Tviol_OENeg_WENeg              OR
                     Tviol_OENeg_WENeg_Write        OR
                     Tviol_OENeg_WENeg_DataPolling  OR
                     Tviol_WENeg_CENeg_hold         OR
                     Tviol_WENeg_CENeg_setup        OR
                     Tviol_CENeg_WENeg_hold         OR
                     Tviol_CENeg_WENeg_setup        OR
                     Tviol_IO0_CENeg                OR
                     Tviol_IO0_WENeg                OR
                     Tviol_IO0_WENeg_Write          OR
                     Tviol_IO0_WENeg_DataPolling    OR
                     Tviol_OENeg_CENeg              OR
                     Pviol_CENeg                    OR
                     Pviol_WENeg                    OR
                     Pviol_OENeg;

        Viol <= Violation;

        ASSERT Violation = '0'
            REPORT InstancePath & partID & ": simulation may be" &
                    " inaccurate due to timing violations"
            SEVERITY WARNING;

    END IF;
    END PROCESS VITALTimingCheck;

    ----------------------------------------------------------------------------
    --  process for FSM state transition
    ----------------------------------------------------------------------------
    StateTransition : PROCESS(next_state)

    BEGIN

        current_state <= next_state;

   END PROCESS StateTransition;

 --latch address on rising edge and data on falling edge of write
    write_dc: PROCESS (WENeg, CENeg, OENeg)
    BEGIN
        IF (WENeg = '0') AND (CENeg = '0') AND (OENeg = '1') THEN
            write <= '1';
        ELSE
            write <= '0';
        END IF;

        IF ((WENeg = '1') AND (CENeg = '0') AND (OENeg = '0') )THEN
            read <= '1';
        ELSE
            read <= '0';
        END IF;

    END PROCESS write_dc;
    ---------------------------------------------------------------------------
    --Latch address on falling edge of WE# or CE# what ever comes later
    --Latches data on rising edge of WE# or CE# what ever comes first
    -- also Write cycle decode
    ---------------------------------------------------------------------------
    BusCycleDecode : PROCESS(A, IOIn, WENeg, CENeg, OENeg, write)
    VARIABLE A_tmp1  : NATURAL RANGE 0 TO AddrRANGE;

    BEGIN
        IF (falling_edge(WENeg) AND CENeg='0' AND OENeg = '1' ) OR
           (falling_edge(CENeg) AND WENeg /= OENeg ) OR
           (falling_edge(OENeg) AND WENeg='1' AND CENeg = '0' ) OR
           ( A'EVENT AND CENeg='0' AND OENeg = '0')
        THEN

            A_tmp1 := to_nat(A(HiAddrBit downto 0));
            Address <= A_tmp1;
        END IF;

        IF (rising_edge(WENeg) OR rising_edge(CENeg)) AND
            write = '1' 
        THEN
            IO_tmp <= IOIn;
        END IF;

    END PROCESS BusCycleDecode;

    ---------------------------------------------------------------------------
    -- Timing control for the Write Cycle
    ---------------------------------------------------------------------------
    WriteTime : PROCESS(WSTART)
        VARIABLE wob      : time;
    BEGIN
        wob  := tdevice_WR;
        IF rising_edge(WSTART) AND WDONE = '1' THEN
            WDONE <= '0', '1' AFTER wob;
        END IF;
    END PROCESS WriteTime;
    ---------------------------------------------------------------------------
    -- Timing control for the Page Write Cycle
    ---------------------------------------------------------------------------
    PageWriteTime : PROCESS(WPSTART)
        VARIABLE wpob      : time;
    BEGIN
        wpob  := tdevice_BLC;
        IF rising_edge(WPSTART) THEN
            WPDONE <= '0', '1' AFTER wpob;
        END IF;
    END PROCESS PageWriteTime;

 ---------------------------------------------------------------------------
    -- Main Behavior Process
    -- combinational process for next state generation
    ---------------------------------------------------------------------------
    StateGen :PROCESS(write, IOIn, Address, CENeg, OENeg, WENeg,
                       write_tmp, WDONE, WPDONE)
        VARIABLE DataByte          : NATURAL RANGE 0 TO MaxData := 0;
    BEGIN
        -----------------------------------------------------------------------
        -- Functionality Section
        -----------------------------------------------------------------------

        IF IOIn'EVENT THEN
            IF IOIn /= "XXXXXXXX" THEN
                DataByte  := to_nat(IOIn);
            END IF;
            write_tmp <= '1', '0' AFTER 1 ns;
         END IF;

        CASE current_state IS
            WHEN IDLE          =>
                IF rising_edge(write) THEN

                    IF ((Address = 16#5555#) AND (DataByte = 16#AA#))THEN
                        next_state <= SDPEN_ENTRY;
                    ELSIF NOT PROT AND 
                    NOT((Address = 16#5555#) AND (DataByte = 16#AA#))  THEN
                        next_state <= WRT;
                    END IF;
                ELSE
                    next_state <= IDLE;
                END IF;

            WHEN WRT      =>
                IF rising_edge(WDONE) THEN
                        next_state <= IDLE;
                END IF;

            WHEN SDPEN_ENTRY       =>
                IF rising_edge(write_tmp) THEN
                    IF ((Address = 16#2AAA#) AND (DataByte = 16#55#))THEN
                        next_state <= SDPEN_LOAD;
                    ELSE
                        next_state <= IDLE;
                    END IF;
                END IF;

            WHEN SDPEN_LOAD       =>
                IF rising_edge(write_tmp) THEN