at28c010.vhd

vhdl cod for ram.For sp3e

    A11_nwv        <= To_UX01(A11_ipd);
    A12_nwv        <= To_UX01(A12_ipd);
    A13_nwv        <= To_UX01(A13_ipd);
    A14_nwv        <= To_UX01(A14_ipd);
    A15_nwv        <= To_UX01(A15_ipd);
    A16_nwv        <= To_UX01(A16_ipd);
    IO0_nwv        <= To_UX01(IO0_ipd);
    IO1_nwv        <= To_UX01(IO1_ipd);
    IO2_nwv        <= To_UX01(IO2_ipd);
    IO3_nwv        <= To_UX01(IO3_ipd);
    IO4_nwv        <= To_UX01(IO4_ipd);
    IO5_nwv        <= To_UX01(IO5_ipd);
    IO6_nwv        <= To_UX01(IO6_ipd);
    IO7_nwv        <= To_UX01(IO7_ipd);

    ---------------------------------------------------------------------------
    -- Main Behavior Block
    ---------------------------------------------------------------------------
    Behavior: BLOCK
        PORT (
            CENeg          : IN    std_ulogic := 'U';
            OENeg          : IN    std_ulogic := 'U';
            WENeg          : IN    std_ulogic := 'U';
            A              : IN    std_logic_vector(16 DOWNTO 0) :=
                                               (OTHERS => 'U');
            IOIn           : IN    std_logic_vector(7 DOWNTO 0) :=
                                               (OTHERS => 'U');
            IOOut          : OUT   std_ulogic_vector(7 DOWNTO 0) :=
                                               (OTHERS => 'Z')
        );
        PORT MAP (
            OENeg     => OENeg_nwv,
            CENeg    => CENeg_nwv,
            WENeg     => WENeg_nwv,
            A(0)      => A0_nwv,
            A(1)      => A1_nwv,
            A(2)      => A2_nwv,
            A(3)      => A3_nwv,
            A(4)      => A4_nwv,
            A(5)      => A5_nwv,
            A(6)      => A6_nwv,
            A(7)      => A7_nwv,
            A(8)      => A8_nwv,
            A(9)      => A9_nwv,
            A(10)     => A10_nwv,
            A(11)     => A11_nwv,
            A(12)     => A12_nwv,
            A(13)     => A13_nwv,
            A(14)     => A14_nwv,
            A(15)     => A15_nwv,
            A(16)     => A16_nwv,
            IOIn(0)   => IO0_nwv,
            IOIn(1)   => IO1_nwv,
            IOIn(2)   => IO2_nwv,
            IOIn(3)   => IO3_nwv,
            IOIn(4)   => IO4_nwv,
            IOIn(5)   => IO5_nwv,
            IOIn(6)   => IO6_nwv,
            IOIn(7)   => IO7_nwv,
            IOOut(0)  => IO0,
            IOOut(1)  => IO1,
            IOOut(2)  => IO2,
            IOOut(3)  => IO3,
            IOOut(4)  => IO4,
            IOOut(5)  => IO5,
            IOOut(6)  => IO6,
            IOOut(7)  => IO7
        );

        --zero delay signals
        SIGNAL DOut_zd    : std_logic_vector(7 downto 0) := (OTHERS => 'Z');

        SIGNAL IOOut_Pass : std_logic_vector(7 downto 0) := (OTHERS => 'Z');

         -- State Machine : State_Type
        TYPE state_type IS (IDLE,
                              WRT,
                              SDPEN_ENTRY,
                              SDPEN_LOAD,
                              SDPEN_PROT,
                              SDPDI_1,
                              SDPDI_2,
                              SDPDI_3,
                              SDPDI_EXIT
                              );

        TYPE WriteBuffer IS ARRAY (0 TO 128) OF INTEGER RANGE -1 TO MaxData;

        TYPE MemArray IS ARRAY (0 TO AddrRANGE) OF INTEGER RANGE -1 TO MaxData;

    ---------------------------------------------------------------------------
    --  memory declaration
    ---------------------------------------------------------------------------
        SHARED VARIABLE Mem           : MemArray := (OTHERS => MaxData);

        SHARED VARIABLE WRITE_BUFFER  : WriteBuffer := (others => 0);

        SHARED VARIABLE PROT              : BOOLEAN;

        -- states
        SIGNAL current_state    : state_type;
        SIGNAL next_state       : state_type;

        --Command Register
        SIGNAL write            : std_logic := '0';
        SIGNAL read             : std_logic := '0';
        SIGNAL write_tmp        : std_logic := '0';

        SIGNAL WEN              : std_logic := '0';

        SIGNAL IO_tmp           : std_logic_vector (7 downto 0)
                                  := (others => '0');

        SIGNAL RDY             : std_logic := '0'; 

        --FSM control signals

        SIGNAL WDONE            : std_logic := '1'; -- Write. Done
        SIGNAL WSTART           : std_logic := '0'; --Start Write

        SIGNAL WPDONE            : std_logic := '1'; -- PageWrite. Done
        SIGNAL WPSTART           : std_logic := '0'; --Start Page Write

        SIGNAL Address          : NATURAL RANGE 0 TO AddrRANGE := 0;

         -- timing check violation
        SIGNAL Viol                : X01 := '0';

        -- Access time variables
        SHARED VARIABLE OPENLATCH    : BOOLEAN;
        SHARED VARIABLE FROMCE       : BOOLEAN;
        SHARED VARIABLE FROMOE       : BOOLEAN;

    BEGIN

    ---------------------------------------------------------------------------
    -- VITAL Timing Checks Procedures
    ---------------------------------------------------------------------------
    VITALTimingCheck: PROCESS(A0_ipd, IO0_ipd, CENeg_ipd, OENeg_ipd, WENeg_ipd)

         -- Timing Check Variables
        VARIABLE Tviol_A0_WENeg                : X01 := '0';
        VARIABLE TD_A0_WENeg                   : VitalTimingDataType;

        VARIABLE Tviol_OENeg_WENeg             : X01 := '0';
        VARIABLE TD_OENeg_WENeg                : VitalTimingDataType;

        VARIABLE Tviol_OENeg_WENeg_Write       : X01 := '0';
        VARIABLE TD_OENeg_WENeg_Write          : VitalTimingDataType;

        VARIABLE Tviol_OENeg_WENeg_DataPolling : X01 := '0';
        VARIABLE TD_OENeg_WENeg_DataPolling    : VitalTimingDataType;

        VARIABLE Tviol_WENeg_CENeg_setup       : X01 := '0';
        VARIABLE TD_WENeg_CENeg_setup          : VitalTimingDataType;

        VARIABLE Tviol_WENeg_CENeg_hold        : X01 := '0';
        VARIABLE TD_WENeg_CENeg_hold           : VitalTimingDataType;

        VARIABLE Tviol_CENeg_WENeg_setup       : X01 := '0';
        VARIABLE TD_CENeg_WENeg_setup          : VitalTimingDataType;

        VARIABLE Tviol_CENeg_WENeg_hold        : X01 := '0';
        VARIABLE TD_CENeg_WENeg_hold           : VitalTimingDataType;

        VARIABLE Tviol_IO0_CENeg               : X01 := '0';
        VARIABLE TD_IO0_CENeg                  : VitalTimingDataType;

        VARIABLE Tviol_IO0_WENeg               : X01 := '0';
        VARIABLE TD_IO0_WENeg                  : VitalTimingDataType;

        VARIABLE Tviol_IO0_WENeg_Write         : X01 := '0';
        VARIABLE TD_IO0_WENeg_Write            : VitalTimingDataType;

        VARIABLE Tviol_IO0_WENeg_DataPolling   : X01 := '0';
        VARIABLE TD_IO0_WENeg_DataPolling      : VitalTimingDataType; 

        VARIABLE Tviol_OENeg_CENeg             : X01 := '0';
        VARIABLE TD_OENeg_CENeg                : VitalTimingDataType;

        VARIABLE Pviol_CENeg      : X01 := '0';
        VARIABLE PD_CENeg         : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_WENeg      : X01 := '0';
        VARIABLE PD_WENeg         : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_OENeg      : X01 := '0';
        VARIABLE PD_OENeg         : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Violation        : X01 := '0';

    BEGIN
    ---------------------------------------------------------------------------
    -- Timing Check Section
    ---------------------------------------------------------------------------
    IF (TimingChecksOn) THEN

        -- Setup/Hold Check between A0 and WE#
        VitalSetupHoldCheck (
            TestSignal      => A0_ipd,
            TestSignalName  => "A0",
            RefSignal       => WENeg_ipd,
            RefSignalName   => "WE",
            SetupHigh       => tsetup_A0_WENeg,
            SetupLow        => tsetup_A0_WENeg,
            HoldHigh        => thold_A0_WENeg,
            HoldLow         => thold_A0_WENeg,
            CheckEnabled    => true,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_A0_WENeg,
            Violation       => Tviol_A0_WENeg
        );

        -- Setup Check between OE# and WE# /
        VitalSetupHoldCheck (
            TestSignal      => OENeg_ipd,
            TestSignalName  => "OE#",
            RefSignal       => WENeg_ipd,
            RefSignalName   => "WE#",
            SetupHigh       => tsetup_OENeg_WENeg,
            CheckEnabled    => true,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_OENeg_WENeg,
            Violation       => Tviol_OENeg_WENeg
        );

         -- Hold Check between OE# and WE# /
        VitalSetupHoldCheck (
            TestSignal      => OENeg_ipd,
            TestSignalName  => "OE#",
            RefSignal       => WENeg_ipd,
            RefSignalName   => "WE#",
            HoldHigh        => thold_OENeg_WENeg_Write_noedge_posedge,
            CheckEnabled    => write = '1' AND NOT rising_edge(read),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_OENeg_WENeg_Write,
            Violation       => Tviol_OENeg_WENeg_Write
        );

         -- Hold Check between OE# and WE# /
        VitalSetupHoldCheck (
            TestSignal      => OENeg_ipd,
            TestSignalName  => "OE#",
            RefSignal       => WENeg_ipd,
            RefSignalName   => "WE#",
            HoldHigh        => thold_OENeg_WENeg_DataPolling_noedge_posedge,
            CheckEnabled    => rising_edge(read) AND write = '1',
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_OENeg_WENeg_DataPolling,
            Violation       => Tviol_OENeg_WENeg_DataPolling
        );

        -- Setup Check between CE# and WE# \
        VitalSetupHoldCheck (
            TestSignal      => CENeg_ipd,
            TestSignalName  => "CE#",
            RefSignal       => WENeg_ipd,
            RefSignalName   => "WE#",
            SetupLow        => tsetup_CENeg_WENeg,
            CheckEnabled    => true,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_CENeg_WENeg_setup,
            Violation       => Tviol_CENeg_WENeg_setup
        );

        -- Hold Check between CE# and WE# /
        VitalSetupHoldCheck (
            TestSignal      => CENeg_ipd,
            TestSignalName  => "CE#",
            RefSignal       => WENeg_ipd,
            RefSignalName   => "WE#",
            HoldLow         => thold_CENeg_WENeg,
            CheckEnabled    => true,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_CENeg_WENeg_hold,
            Violation       => Tviol_CENeg_WENeg_hold
        );

        -- Setup Check between WE# and CE# \
        VitalSetupHoldCheck (
            TestSignal      => WENeg_ipd,
            TestSignalName  => "WE#",
            RefSignal       => CENeg_ipd,
            RefSignalName   => "CE#",