at28c010.vhd

vhdl cod for ram.For sp3e

-------------------------------------------------------------------------------
--  File Name: at28c010.vhd
-------------------------------------------------------------------------------
--  Copyright (C) 2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:        | mod date: |  changes made:
--    V1.0     D.Beatovic       07 Aug 21   Inital Release
--
-------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    RAM
--  Technology: EEPROM
--  Part:       at28c010
--
--   Description: 1M (128k x 8) Paged Paralel EEPROM
-------------------------------------------------------------------------------
--  Known Bugs:
--
-------------------------------------------------------------------------------
LIBRARY IEEE;  USE IEEE.std_logic_1164.ALL;
               USE STD.textio.ALL;
               USE IEEE.VITAL_timing.ALL;
               USE IEEE.VITAL_primitives.ALL;

LIBRARY FMF;   USE FMF.gen_utils.ALL;
               USE FMF.conversions.ALL;
-------------------------------------------------------------------------------
-- ENTITY DECLARATION
-------------------------------------------------------------------------------
ENTITY at28c010 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A0            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A13           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A14           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A15           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A16           : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO0           : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO1           : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO2           : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO3           : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO4           : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO5           : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO6           : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO7           : VitalDelayType01 := VitalZeroDelay01;
        tipd_CENeg         : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg         : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENeg         : VitalDelayType01 := VitalZeroDelay01;

        -- tpd delays
        tpd_A0_IO0         : VitalDelayType01 := UnitDelay01;--tACC
        tpd_CENeg_IO0      : VitalDelayType01Z := UnitDelay01Z;--tCE,tDF
        tpd_OENeg_IO0      : VitalDelayType01Z := UnitDelay01Z;--tOE, tDF

        --tsetup values
        tsetup_A0_WENeg       : VitalDelayType := UnitDelay;  --tAS
        tsetup_OENeg_WENeg    : VitalDelayType := UnitDelay;  --tOES
        tsetup_CENeg_WENeg    : VitalDelayType := UnitDelay;  --tCS
        tsetup_WENeg_CENeg    : VitalDelayType := UnitDelay;  --tCS
        tsetup_IO0_WENeg      : VitalDelayType := UnitDelay;  --tDS
        tsetup_IO0_CENeg      : VitalDelayType := UnitDelay;  --tDS

        --thold values
        thold_A0_WENeg        : VitalDelayType := UnitDelay;  --tAH
        thold_CENeg_WENeg     : VitalDelayType := UnitDelay;  --tCH
        thold_WENeg_CENeg     : VitalDelayType := UnitDelay;  --tCH
        thold_IO0_WENeg_Write_noedge_posedge 
                              : VitalDelayType := UnitDelay;  --tDH
        thold_OENeg_WENeg_Write_noedge_posedge  
                              : VitalDelayType := UnitDelay;  --tOEH
        thold_IO0_WENeg_DataPolling_noedge_posedge 
                              : VitalDelayType := UnitDelay;  --tDH
        thold_OENeg_WENeg_DataPolling_noedge_posedge  
                              : VitalDelayType := UnitDelay;  --tOEH
        thold_OENeg_CENeg     : VitalDelayType := UnitDelay;  --tDH
        thold_IO0_WENeg       : VitalDelayType := UnitDelay;  --tDH
        thold_IO0_CENeg       : VitalDelayType := UnitDelay;  --tDH

        --tpw values: pulse width
        tpw_CENeg_negedge     : VitalDelayType := UnitDelay; --tWP
        tpw_WENeg_negedge     : VitalDelayType := UnitDelay; --tWP
        tpw_WENeg_posedge     : VitalDelayType := UnitDelay; --tWPH
        tpw_OENeg_DataPolling_posedge
                              : VitalDelayType := UnitDelay; --tOEHP

        -- tdevice values: values for internal delays
            -- Write cycle time
        tdevice_WR           : VitalDelayType    := 10 ms;   --tWC
            -- Byte Load cycle time
        tdevice_BLC          : VitalDelayType   := 150 us;   --tBLC

        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- memory file to be loaded
        mem_file_name       : STRING    := "at28c010.mem";

        UserPreload         : BOOLEAN   := TRUE;

        -- For FMF SDF technology file usage
        TimingModel         : STRING
    );
    PORT (
        A0              : IN     std_ulogic := 'U';
        A1              : IN     std_ulogic := 'U';
        A2              : IN     std_ulogic := 'U';
        A3              : IN     std_ulogic := 'U';
        A4              : IN     std_ulogic := 'U';
        A5              : IN     std_ulogic := 'U';
        A6              : IN     std_ulogic := 'U';
        A7              : IN     std_ulogic := 'U';
        A8              : IN     std_ulogic := 'U';
        A9              : IN     std_ulogic := 'U';
        A10             : IN     std_ulogic := 'U';
        A11             : IN     std_ulogic := 'U';
        A12             : IN     std_ulogic := 'U';
        A13             : IN     std_ulogic := 'U';
        A14             : IN     std_ulogic := 'U';
        A15             : IN     std_ulogic := 'U';
        A16             : IN     std_ulogic := 'U';
        CENeg           : IN     std_ulogic := 'U';
        OENeg           : IN     std_ulogic := 'U';
        WENeg           : IN     std_ulogic := 'U';
        IO0             : INOUT std_ulogic := 'U';
        IO1             : INOUT std_ulogic := 'U';
        IO2             : INOUT std_ulogic := 'U';
        IO3             : INOUT std_ulogic := 'U';
        IO4             : INOUT std_ulogic := 'U';
        IO5             : INOUT std_ulogic := 'U';
        IO6             : INOUT std_ulogic := 'U';
        IO7             : INOUT std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of at28c010 : ENTITY IS TRUE;
END at28c010;

-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of at28c010 IS
    ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT PartID        : STRING  := "at28c010";
    CONSTANT MaxData       : NATURAL := 16#FF#; --255
    CONSTANT HiAddrBit     : NATURAL := 16;
    CONSTANT AddrRANGE     : NATURAL := 16#1FFFF#;

-- interconnect path delay signals
    SIGNAL A0_ipd         : std_ulogic := 'U';
    SIGNAL A1_ipd         : std_ulogic := 'U';
    SIGNAL A2_ipd         : std_ulogic := 'U';
    SIGNAL A3_ipd         : std_ulogic := 'U';
    SIGNAL A4_ipd         : std_ulogic := 'U';
    SIGNAL A5_ipd         : std_ulogic := 'U';
    SIGNAL A6_ipd         : std_ulogic := 'U';
    SIGNAL A7_ipd         : std_ulogic := 'U';
    SIGNAL A8_ipd         : std_ulogic := 'U';
    SIGNAL A9_ipd         : std_ulogic := 'U';
    SIGNAL A10_ipd        : std_ulogic := 'U';
    SIGNAL A11_ipd        : std_ulogic := 'U';
    SIGNAL A12_ipd        : std_ulogic := 'U';
    SIGNAL A13_ipd        : std_ulogic := 'U';
    SIGNAL A14_ipd        : std_ulogic := 'U';
    SIGNAL A15_ipd        : std_ulogic := 'U';
    SIGNAL A16_ipd        : std_ulogic := 'U';
    SIGNAL IO0_ipd        : std_ulogic := 'U';
    SIGNAL IO1_ipd        : std_ulogic := 'U';
    SIGNAL IO2_ipd        : std_ulogic := 'U';
    SIGNAL IO3_ipd        : std_ulogic := 'U';
    SIGNAL IO4_ipd        : std_ulogic := 'U';
    SIGNAL IO5_ipd        : std_ulogic := 'U';
    SIGNAL IO6_ipd        : std_ulogic := 'U';
    SIGNAL IO7_ipd        : std_ulogic := 'U';
    SIGNAL CENeg_ipd      : std_ulogic := 'U';
    SIGNAL OENeg_ipd      : std_ulogic := 'U';
    SIGNAL WENeg_ipd      : std_ulogic := 'U';

    SIGNAL A0_nwv         : std_ulogic := 'U';
    SIGNAL A1_nwv         : std_ulogic := 'U';
    SIGNAL A2_nwv         : std_ulogic := 'U';
    SIGNAL A3_nwv         : std_ulogic := 'U';
    SIGNAL A4_nwv         : std_ulogic := 'U';
    SIGNAL A5_nwv         : std_ulogic := 'U';
    SIGNAL A6_nwv         : std_ulogic := 'U';
    SIGNAL A7_nwv         : std_ulogic := 'U';
    SIGNAL A8_nwv         : std_ulogic := 'U';
    SIGNAL A9_nwv         : std_ulogic := 'U';
    SIGNAL A10_nwv        : std_ulogic := 'U';
    SIGNAL A11_nwv        : std_ulogic := 'U';
    SIGNAL A12_nwv        : std_ulogic := 'U';
    SIGNAL A13_nwv        : std_ulogic := 'U';
    SIGNAL A14_nwv        : std_ulogic := 'U';
    SIGNAL A15_nwv        : std_ulogic := 'U';
    SIGNAL A16_nwv        : std_ulogic := 'U';
    SIGNAL IO0_nwv        : std_ulogic := 'U';
    SIGNAL IO1_nwv        : std_ulogic := 'U';
    SIGNAL IO2_nwv        : std_ulogic := 'U';
    SIGNAL IO3_nwv        : std_ulogic := 'U';
    SIGNAL IO4_nwv        : std_ulogic := 'U';
    SIGNAL IO5_nwv        : std_ulogic := 'U';
    SIGNAL IO6_nwv        : std_ulogic := 'U';
    SIGNAL IO7_nwv        : std_ulogic := 'U';
    SIGNAL CENeg_nwv      : std_ulogic := 'U';
    SIGNAL OENeg_nwv      : std_ulogic := 'U';
    SIGNAL WENeg_nwv      : std_ulogic := 'U';

     ---  internal delays
    SIGNAL WR_in           : std_ulogic := '0';
    SIGNAL WR_out          : std_ulogic := '0';

    SIGNAL BLC_in           : std_ulogic := '0';
    SIGNAL BLC_out          : std_ulogic := '0';

BEGIN
    ---------------------------------------------------------------------------
    -- Internal Delays
    ---------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays
    WR     :VitalBuf(WR_out,   WR_in,       (tdevice_WR     ,UnitDelay));
    BLC    :VitalBuf(BLC_out,  BLC_in,      (tdevice_BLC    ,UnitDelay));
    ---------------------------------------------------------------------------
    -- Wire Delays
    ---------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1  : VitalWireDelay (CENeg_ipd,   CENeg, tipd_CENeg);
        w_2  : VitalWireDelay (OENeg_ipd,   OENeg, tipd_OENeg);
        w_3  : VitalWireDelay (WENeg_ipd,   WENeg, tipd_WENeg);
        w_4  : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_5  : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_6  : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_7  : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_8  : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_9  : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_10 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_11 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_12 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_13 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_14 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_15 : VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_16 : VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_17 : VitalWireDelay (A13_ipd, A13, tipd_A13);
        w_18 : VitalWireDelay (A14_ipd, A14, tipd_A14);
        w_19 : VitalWireDelay (A15_ipd, A15, tipd_A15);
        w_20 : VitalWireDelay (A16_ipd, A16, tipd_A16);
        w_21 : VitalWireDelay (IO0_ipd, IO0, tipd_IO0);
        w_22 : VitalWireDelay (IO1_ipd, IO1, tipd_IO1);
        w_23 : VitalWireDelay (IO2_ipd, IO2, tipd_IO2);
        w_24 : VitalWireDelay (IO3_ipd, IO3, tipd_IO3);
        w_25 : VitalWireDelay (IO4_ipd, IO4, tipd_IO4);
        w_26 : VitalWireDelay (IO5_ipd, IO5, tipd_IO5);
        w_27 : VitalWireDelay (IO6_ipd, IO6, tipd_IO6);
        w_28 : VitalWireDelay (IO7_ipd, IO7, tipd_IO7);

    END BLOCK;
    OENeg_nwv      <= To_UX01(OENeg_ipd);
    CENeg_nwv      <= To_UX01(CENeg_ipd);
    WENeg_nwv      <= To_UX01(WENeg_ipd);
    A0_nwv         <= To_UX01(A0_ipd);
    A1_nwv         <= To_UX01(A1_ipd);
    A2_nwv         <= To_UX01(A2_ipd);
    A3_nwv         <= To_UX01(A3_ipd);
    A4_nwv         <= To_UX01(A4_ipd);
    A5_nwv         <= To_UX01(A5_ipd);
    A6_nwv         <= To_UX01(A6_ipd);
    A7_nwv         <= To_UX01(A7_ipd);
    A8_nwv         <= To_UX01(A8_ipd);
    A9_nwv         <= To_UX01(A9_ipd);
    A10_nwv        <= To_UX01(A10_ipd);