cy7c1360.ftm

来自「vhdl cod for ram.For sp3e」· FTM 代码 · 共 537 行 · 第 1/2 页

    (PERIOD (posedge CLK) (10.00))
    (WIDTH (posedge CLK)(3.00))
    (WIDTH (negedge CLK)(3.00))
    (SETUP A0 CLK (2.00))
    (SETUP DQA0 CLK (2.00))
    (SETUP ADVNeg CLK (2.00))
    (SETUP ADSCNeg CLK (2.00))
    (SETUP BWANeg CLK (2.00))
    (SETUP CE2 CLK (2.00))
    (HOLD A0 CLK (0.50))
    (HOLD DQA0 CLK (0.50))
    (HOLD ADSCNeg CLK (0.50))
    (HOLD BWANeg CLK (0.50))
    (HOLD ADVNeg CLK (0.50))
    (HOLD CE2 CLK (0.50))
  )
</TIMING></FMFTIME>
<FMFTIME>
GS88136AT-250<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
GS88136AT-250I<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
<COMMENT>The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (1.50:2.00:2.50) (1.50:2.00:2.50) (1.50:2.00:2.30) (1.50:2.00:2.50) (1.50:2.00:2.30) (1.50:2.00:2.50))
    (IOPATH OENeg DQA0 () () (0.77:1.53:2.30) (0.77:1.53:2.30) (0.77:1.53:2.30) (0.77:1.53:2.30))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (4.00))
    (WIDTH (posedge CLK)(1.30))
    (WIDTH (negedge CLK)(1.50))
    (SETUP A0 CLK (1.20))
    (SETUP DQA0 CLK (1.20))
    (SETUP ADVNeg CLK (1.20))
    (SETUP ADSCNeg CLK (1.20))
    (SETUP BWANeg CLK (1.20))
    (SETUP CE2 CLK (1.20))
    (HOLD A0 CLK (0.20))
    (HOLD DQA0 CLK (0.20))
    (HOLD ADSCNeg CLK (0.20))
    (HOLD BWANeg CLK (0.20))
    (HOLD ADVNeg CLK (0.20))
    (HOLD CE2 CLK (0.20))
  )
</TIMING></FMFTIME>
<FMFTIME>
GS88136AT-225<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
GS88136AT-225I<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
<COMMENT>The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (1.50:2.10:2.70) (1.50:2.10:2.70) (1.50:2.10:2.50) (1.50:2.10:2.70) (1.50:2.10:2.50) (1.50:2.10:2.70))
    (IOPATH OENeg DQA0 () () (0.83:1.67:2.50) (0.83:1.67:2.50) (0.83:1.67:2.50) (0.83:1.67:2.50))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (4.40))
    (WIDTH (posedge CLK)(1.30))
    (WIDTH (negedge CLK)(1.50))
    (SETUP A0 CLK (1.30))
    (SETUP DQA0 CLK (1.30))
    (SETUP ADVNeg CLK (1.30))
    (SETUP ADSCNeg CLK (1.30))
    (SETUP BWANeg CLK (1.30))
    (SETUP CE2 CLK (1.30))
    (HOLD A0 CLK (0.30))
    (HOLD DQA0 CLK (0.30))
    (HOLD ADSCNeg CLK (0.30))
    (HOLD BWANeg CLK (0.30))
    (HOLD ADVNeg CLK (0.30))
    (HOLD CE2 CLK (0.30))
  )
</TIMING></FMFTIME>
<FMFTIME>
GS88136AT-200<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
GS88136AT-200I<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
<COMMENT>The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (1.50:2.25:3.00) (1.50:2.25:3.00) (1.50:2.40:3.00) (1.50:2.25:3.00) (1.50:2.40:3.00) (1.50:2.25:3.00))
    (IOPATH OENeg DQA0 () () (1.00:2.00:3.00) (1.07:2.13:3.20) (1.00:2.00:3.00) (1.07:2.13:3.20))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (5.00))
    (WIDTH (posedge CLK)(1.30))
    (WIDTH (negedge CLK)(1.50))
    (SETUP A0 CLK (1.40))
    (SETUP DQA0 CLK (1.40))
    (SETUP ADVNeg CLK (1.40))
    (SETUP ADSCNeg CLK (1.40))
    (SETUP BWANeg CLK (1.40))
    (SETUP CE2 CLK (1.40))
    (HOLD A0 CLK (0.40))
    (HOLD DQA0 CLK (0.40))
    (HOLD ADSCNeg CLK (0.40))
    (HOLD BWANeg CLK (0.40))
    (HOLD ADVNeg CLK (0.40))
    (HOLD CE2 CLK (0.40))
  )
</TIMING></FMFTIME>
<FMFTIME>
GS88136AT-166<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
GS88136AT-166I<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
<COMMENT>The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (1.50:2.45:3.40) (1.50:2.45:3.40) (1.50:2.40:3.00) (1.50:2.45:3.40) (1.50:2.40:3.00) (1.50:2.45:3.40))
    (IOPATH OENeg DQA0 () () (1.00:2.00:3.00) (1.17:2.33:3.50) (1.00:2.00:3.00) (1.17:2.33:3.50))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (6.00))
    (WIDTH (posedge CLK)(1.30))
    (WIDTH (negedge CLK)(1.50))
    (SETUP A0 CLK (1.50))
    (SETUP DQA0 CLK (1.50))
    (SETUP ADVNeg CLK (1.50))
    (SETUP ADSCNeg CLK (1.50))
    (SETUP BWANeg CLK (1.50))
    (SETUP CE2 CLK (1.50))
    (HOLD A0 CLK (0.50))
    (HOLD DQA0 CLK (0.50))
    (HOLD ADSCNeg CLK (0.50))
    (HOLD BWANeg CLK (0.50))
    (HOLD ADVNeg CLK (0.50))
    (HOLD CE2 CLK (0.50))
  )
</TIMING></FMFTIME>
<FMFTIME>
GS88136AT-150<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
GS88136AT-150I<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
<COMMENT>The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (1.50:2.65:3.80) (1.50:2.65:3.80) (1.50:2.40:3.00) (1.50:2.65:3.80) (1.50:2.40:3.00) (1.50:2.65:3.80))
    (IOPATH OENeg DQA0 () () (1.00:2.00:3.00) (1.27:2.53:3.80) (1.00:2.00:3.00) (1.27:2.53:3.80))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (6.70))
    (WIDTH (posedge CLK)(1.50))
    (WIDTH (negedge CLK)(1.70))
    (SETUP A0 CLK (1.50))
    (SETUP DQA0 CLK (1.50))
    (SETUP ADVNeg CLK (1.50))
    (SETUP ADSCNeg CLK (1.50))
    (SETUP BWANeg CLK (1.50))
    (SETUP CE2 CLK (1.50))
    (HOLD A0 CLK (0.50))
    (HOLD DQA0 CLK (0.50))
    (HOLD ADSCNeg CLK (0.50))
    (HOLD BWANeg CLK (0.50))
    (HOLD ADVNeg CLK (0.50))
    (HOLD CE2 CLK (0.50))
  )
</TIMING></FMFTIME>
<FMFTIME>
GS88136AT-133<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
GS88136AT-133I<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>
<COMMENT>The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (1.50:2.75:4.00) (1.50:2.75:4.00) (1.50:2.40:3.00) (1.50:2.75:4.00) (1.50:2.40:3.00) (1.50:2.75:4.00))
    (IOPATH OENeg DQA0 () () (1.00:2.00:3.00) (1.33:2.67:4.00) (1.00:2.00:3.00) (1.33:2.67:4.00))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (7.50))
    (WIDTH (posedge CLK)(1.70))
    (WIDTH (negedge CLK)(2.00))
    (SETUP A0 CLK (1.50))
    (SETUP DQA0 CLK (1.50))
    (SETUP ADVNeg CLK (1.50))
    (SETUP ADSCNeg CLK (1.50))
    (SETUP BWANeg CLK (1.50))
    (SETUP CE2 CLK (1.50))
    (HOLD A0 CLK (0.50))
    (HOLD DQA0 CLK (0.50))
    (HOLD ADSCNeg CLK (0.50))
    (HOLD BWANeg CLK (0.50))
    (HOLD ADVNeg CLK (0.50))
    (HOLD CE2 CLK (0.50))
  )
</TIMING></FMFTIME>
<FMFTIME>
CY7C1360B-225AC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
CY7C1360B-225AJC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
CY7C1360B-225BGC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
CY7C1360B-225BZC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
<COMMENT>The values listed are for VDD=3.135Vto3.6V, commercial TA=0Cto+70C, VDDQ=3.3V</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (1.25:2.00:2.80) (1.25:2.00:2.80) (1.25:2.00:2.80) (1.25:2.00:2.80) (1.25:2.00:2.80) (1.25:2.00:2.80))
    (IOPATH OENeg DQA0 () () (0.00:1.40:2.80) (0.00:1.40:2.80) (0.00:1.40:2.80) (0.00:1.40:2.80))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (4.40))
    (WIDTH (posedge CLK)(1.80))
    (WIDTH (negedge CLK)(1.80))
    (SETUP A0 CLK (1.40))
    (SETUP DQA0 CLK (1.40))
    (SETUP ADVNeg CLK (1.40))
    (SETUP ADSCNeg CLK (1.40))
    (SETUP BWANeg CLK (1.40))
    (SETUP CE2 CLK (1.40))
    (HOLD A0 CLK (0.30))
    (HOLD DQA0 CLK (0.40))
    (HOLD ADSCNeg CLK (0.40))
    (HOLD BWANeg CLK (0.40))
    (HOLD ADVNeg CLK (0.40))
    (HOLD CE2 CLK (0.40))
  )
</TIMING></FMFTIME>
<FMFTIME>
CY7C1360B-200AC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
CY7C1360B-200AJC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
CY7C1360B-200BGC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
CY7C1360B-200BZC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
<COMMENT>The values listed are for VDD=3.135Vto3.6V, commercial TA=0Cto+70C, VDDQ=3.3V</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (1.25:2.15:3.00) (1.25:2.15:3.00) (1.25:2.15:3.00) (1.25:2.15:3.00) (1.25:2.15:3.00) (1.25:2.15:3.00))
    (IOPATH OENeg DQA0 () () (0.00:1.50:3.00) (1.00:2.00:3.00) (0.00:1.50:3.00) (1.00:2.00:3.00))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (5.00))
    (WIDTH (posedge CLK)(2.00))
    (WIDTH (negedge CLK)(2.00))
    (SETUP A0 CLK (1.50))
    (SETUP DQA0 CLK (1.50))
    (SETUP ADVNeg CLK (1.50))
    (SETUP ADSCNeg CLK (1.50))
    (SETUP BWANeg CLK (1.50))
    (SETUP CE2 CLK (1.50))
    (HOLD A0 CLK (0.50))
    (HOLD DQA0 CLK (0.50))
    (HOLD ADSCNeg CLK (0.50))
    (HOLD BWANeg CLK (0.50))
    (HOLD ADVNeg CLK (0.50))
    (HOLD CE2 CLK (0.50))
  )
</TIMING></FMFTIME>
<FMFTIME>
CY7C1360B-166AC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
CY7C1360B-166AJC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
CY7C1360B-166BGC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
CY7C1360B-166BZC<SOURCE>Cypress Semiconductor Corporation, 38-05291, Rev C, April 9, 2004</SOURCE>
<COMMENT>The values listed are for VDD=3.135Vto3.6V, commercial TA=0Cto+70C, VDDQ=3.3V</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (1.25:2.40:3.50) (1.25:2.40:3.50) (1.25:2.40:3.50) (1.25:2.40:3.50) (1.25:2.40:3.50) (1.25:2.40:3.50))
    (IOPATH OENeg DQA0 () () (0.00:1.75:3.50) (1.17:2.33:3.50) (0.00:1.75:3.50) (1.17:2.33:3.50))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (6.00))
    (WIDTH (posedge CLK)(2.40))
    (WIDTH (negedge CLK)(2.40))
    (SETUP A0 CLK (1.50))
    (SETUP DQA0 CLK (1.50))
    (SETUP ADVNeg CLK (1.50))
    (SETUP ADSCNeg CLK (1.50))
    (SETUP BWANeg CLK (1.50))
    (SETUP CE2 CLK (1.50))
    (HOLD A0 CLK (0.50))
    (HOLD DQA0 CLK (0.50))
    (HOLD ADSCNeg CLK (0.50))
    (HOLD BWANeg CLK (0.50))
    (HOLD ADVNeg CLK (0.50))
    (HOLD CE2 CLK (0.50))
  )
</TIMING></FMFTIME>
</BODY></FTML>