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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for idt71v65903 Parts</TITLE><BODY><REVISION.HISTORY>version: | author: | mod date: | changes made: V1.0 R. Munden 01 Dec 15 Initial release</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>idt71v65903<FMFTIME>CY7C1357A1-100AC<SOURCE>Cypress Semiconductor Preliminary Datasheet May 24, 2001</SOURCE>CY7C1357A1-100BG<SOURCE>Cypress Semiconductor Preliminary Datasheet May 24, 2001</SOURCE><COMMENT>The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>parameters missing from the datasheet were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2:5:8) (2:5:8) (2:3:3.5) (3:5:8) (2:3:3.5) (3:5:8)) (IOPATH OENeg DQA0 () () (2:3:3.5) (0:3:4) (2:3:3.5) (0:3:4)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (2:2:2)) (SETUP A0 CLK (2:2:2)) (SETUP DQA0 CLK (2:2:2)) (SETUP R CLK (2:2:2)) (SETUP ADV CLK (2:2:2)) (SETUP CE2 CLK (2:2:2)) (SETUP BWANeg CLK (2:2:2)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (3.5:3.5:3.5)) (WIDTH (negedge CLK) (3.5:3.5:3.5)) (PERIOD (posedge CLK) (10:10:10)) )</TIMING></FMFTIME><FMFTIME>CY7C1357A-100AC<SOURCE>Cypress Semiconductor Preliminary Datasheet May 24, 2001</SOURCE>CY7C1357A-100BG<SOURCE>Cypress Semiconductor Preliminary Datasheet May 24, 2001</SOURCE><COMMENT>The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>parameters missing from the datasheet were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2:5:7.5) (2:5:7.5) (2:3:3.5) (3:5:7.5) (2:3:3.5) (3:5:7.5)) (IOPATH OENeg DQA0 () () (2:3:3.5) (0:3:4) (2:3:3.5) (0:3:4)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (1.8:1.8:1.8)) (SETUP A0 CLK (1.8:1.8:1.8)) (SETUP DQA0 CLK (1.8:1.8:1.8)) (SETUP R CLK (1.8:1.8:1.8)) (SETUP ADV CLK (1.8:1.8:1.8)) (SETUP CE2 CLK (1.8:1.8:1.8)) (SETUP BWANeg CLK (1.8:1.8:1.8)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (3.5:3.5:3.5)) (WIDTH (negedge CLK) (3.5:3.5:3.5)) (PERIOD (posedge CLK) (10:10:10)) )</TIMING></FMFTIME><FMFTIME>CY7C1357A-117AC<SOURCE>Cypress Semiconductor Preliminary Datasheet May 24, 2001</SOURCE>CY7C1357A-117BG<SOURCE>Cypress Semiconductor Preliminary Datasheet May 24, 2001</SOURCE><COMMENT>The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>parameters missing from the datasheet were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2:4:7) (2:4:7) (2:3:3.5) (3:4:7) (2:3:3.5) (3:4:7)) (IOPATH OENeg DQA0 () () (2:3:3.5) (0:3:3.5) (2:3:3.5) (0:3:3.5)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (1.5:1.5:1.5)) (SETUP A0 CLK (1.5:1.5:1.5)) (SETUP DQA0 CLK (1.5:1.5:1.5)) (SETUP R CLK (1.5:1.5:1.5)) (SETUP ADV CLK (1.5:1.5:1.5)) (SETUP CE2 CLK (1.5:1.5:1.5)) (SETUP BWANeg CLK (1.5:1.5:1.5)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (3:3:3)) (WIDTH (negedge CLK) (3:3:3)) (PERIOD (posedge CLK) (8.5:8.5:8.5)) )</TIMING></FMFTIME><FMFTIME>CY7C1357A-133AC<SOURCE>Cypress Semiconductor Preliminary Datasheet May 24, 2001</SOURCE>CY7C1357A-133BG<SOURCE>Cypress Semiconductor Preliminary Datasheet May 24, 2001</SOURCE><COMMENT>The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>parameters missing from the datasheet were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2:4:6.5) (2:4:6.5) (2:3:3.5) (3:5:6.5) (2:3:3.5) (3:5:6.5)) (IOPATH OENeg DQA0 () () (2:3:3.5) (0:3:3.5) (2:3:3.5) (0:3:3.5)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (1.5:1.5:1.5)) (SETUP A0 CLK (1.5:1.5:1.5)) (SETUP DQA0 CLK (1.5:1.5:1.5)) (SETUP R CLK (1.5:1.5:1.5)) (SETUP ADV CLK (1.5:1.5:1.5)) (SETUP CE2 CLK (1.5:1.5:1.5)) (SETUP BWANeg CLK (1.5:1.5:1.5)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (2.5:2.5:2.5)) (WIDTH (negedge CLK) (2.5:2.5:2.5)) (PERIOD (posedge CLK) (7.5:7.5:7.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V65903S75BG<SOURCE>IDT Datasheet DSC-5298/01 November 2000</SOURCE>IDT71V65903S75BQ<SOURCE>IDT Datasheet DSC-5298/01 November 2000</SOURCE>IDT71V65903S75PF<SOURCE>IDT Datasheet DSC-5298/01 November 2000</SOURCE><COMMENT>The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>parameters missing from the datasheet were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2:5:7.5) (2:5:7.5) (2:4:5) (3:5:7.5) (2:4:5) (3:5:7.5)) (IOPATH OENeg DQA0 () () (2:4:5) (0:4:5) (2:4:5) (0:4:5)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (2:2:2)) (SETUP A0 CLK (2:2:2)) (SETUP DQA0 CLK (2:2:2)) (SETUP R CLK (2:2:2)) (SETUP ADV CLK (2:2:2)) (SETUP CE2 CLK (2:2:2)) (SETUP BWANeg CLK (2:2:2)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (2.5:2.5:2.5)) (WIDTH (negedge CLK) (2.5:2.5:2.5)) (PERIOD (posedge CLK) (10:10:10)) )</TIMING></FMFTIME><FMFTIME>IDT71V65903S80BG<SOURCE>IDT Datasheet DSC-5298/01 November 2000</SOURCE>IDT71V65903S80BQ<SOURCE>IDT Datasheet DSC-5298/01 November 2000</SOURCE>IDT71V65903S80PF<SOURCE>IDT Datasheet DSC-5298/01 November 2000</SOURCE><COMMENT>The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>parameters missing from the datasheet were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2:5:8) (2:5:8) (2:4:5) (3:6:8) (2:4:6) (3:6:8)) (IOPATH OENeg DQA0 () () (2:4:5) (0:4:5) (2:4:5) (0:4:5)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (2:2:2)) (SETUP A0 CLK (2:2:2)) (SETUP DQA0 CLK (2:2:2)) (SETUP R CLK (2:2:2)) (SETUP ADV CLK (2:2:2)) (SETUP CE2 CLK (2:2:2)) (SETUP BWANeg CLK (2:2:2)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (2.7:2.7:2.7)) (WIDTH (negedge CLK) (2.7:2.7:2.7)) (PERIOD (posedge CLK) (10.5:10.5:10.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V65903S85BG<SOURCE>IDT Datasheet DSC-5298/01 November 2000</SOURCE>IDT71V65903S85BQ<SOURCE>IDT Datasheet DSC-5298/01 November 2000</SOURCE>IDT71V65903S85PF<SOURCE>IDT Datasheet DSC-5298/01 November 2000</SOURCE><COMMENT>The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>parameters missing from the datasheet were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2:6:8.5) (2:6:8.5) (2:4:5) (3:6:8.5) (2:4:5) (3:6:8.5)) (IOPATH OENeg DQA0 () () (2:4:5) (0:4:5) (2:4:5) (0:4:5)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (2:2:2)) (SETUP A0 CLK (2:2:2)) (SETUP DQA0 CLK (2:2:2)) (SETUP R CLK (2:2:2)) (SETUP ADV CLK (2:2:2)) (SETUP CE2 CLK (2:2:2)) (SETUP BWANeg CLK (2:2:2)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (3:3:3)) (WIDTH (negedge CLK) (3:3:3)) (PERIOD (posedge CLK) (11:11:11)) )</TIMING></FMFTIME><FMFTIME>MT55L512L18FB-10<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512L18FF-10<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512L18FT-10<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512V18FB-10<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512V18FF-10<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512V18FT-10<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE><COMMENT>The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>parameters missing from the datasheet were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (3:5:7.5) (3:5:7.5) (3:4:5) (3:5:7.5) (3:4:5) (3:5:7.5)) (IOPATH OENeg DQA0 () () (3:4:5) (0:4:5) (3:4:5) (0:4:5)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (2:2:2)) (SETUP A0 CLK (2:2:2)) (SETUP DQA0 CLK (2:2:2)) (SETUP R CLK (2:2:2)) (SETUP ADV CLK (2:2:2)) (SETUP CE2 CLK (2:2:2)) (SETUP BWANeg CLK (2:2:2)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (2.5:2.5:2.5)) (WIDTH (negedge CLK) (2.5:2.5:2.5)) (PERIOD (posedge CLK) (10:10:10)) )</TIMING></FMFTIME><FMFTIME>MT55L512L18FB-11<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512L18FF-11<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512L18FT-11<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512V18FB-11<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512V18FF-11<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512V18FT-11<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE><COMMENT>The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>parameters missing from the datasheet were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (3:6:8.5) (3:6:8.5) (3:4:5) (3:6:8.5) (3:4:5) (3:6:8.5)) (IOPATH OENeg DQA0 () () (3:4:5) (0:4:5) (3:4:5) (0:4:5)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (2.2:2.2:2.2)) (SETUP A0 CLK (2.2:2.2:2.2)) (SETUP DQA0 CLK (2.2:2.2:2.2)) (SETUP R CLK (2.2:2.2:2.2)) (SETUP ADV CLK (2.2:2.2:2.2)) (SETUP CE2 CLK (2.2:2.2:2.2)) (SETUP BWANeg CLK (2.2:2.2:2.2)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (3:3:3)) (WIDTH (negedge CLK) (3:3:3)) (PERIOD (posedge CLK) (11:11:11)) )</TIMING></FMFTIME><FMFTIME>MT55L512L18FB-12<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512L18FF-12<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512L18FT-12<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512V18FB-12<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512V18FF-12<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE>MT55L512V18FT-12<SOURCE>Micron Technology MT55L512L18F_2.p65 Rev. 6/01</SOURCE><COMMENT>The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>parameters missing from the datasheet were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (3:6:9) (3:6:9) (3:4:5) (3:6:9) (3:4:5) (3:6:9)) (IOPATH OENeg DQA0 () () (3:4:5) (0:4:5) (3:4:5) (0:4:5)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (2.5:2.5:2.5)) (SETUP A0 CLK (2.5:2.5:2.5)) (SETUP DQA0 CLK (2.5:2.5:2.5)) (SETUP R CLK (2.5:2.5:2.5)) (SETUP ADV CLK (2.5:2.5:2.5)) (SETUP CE2 CLK (2.5:2.5:2.5)) (SETUP BWANeg CLK (2.5:2.5:2.5)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (3:3:3)) (WIDTH (negedge CLK) (3:3:3)) (PERIOD (posedge CLK) (12:12:12)) )</TIMING></FMFTIME></BODY></FTML>
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