edj1316ba.vhd

vhdl cod for ram.For sp3e

        SHARED VARIABLE mrs_cnt : natural;

        SIGNAL mrs_active : std_logic := '0';

        SIGNAL preamble_check : boolean := FALSE;
        SIGNAL postamble_check : boolean := FALSE;
        SIGNAL skew_check : boolean := FALSE;

        FUNCTION bool_to_nat(tm : boolean)
        RETURN natural IS
            VARIABLE Temp : natural;
        BEGIN
            Temp := 0;
            IF tm THEN
                Temp := 1;
            END IF;
            RETURN Temp;
        END bool_to_nat;

    BEGIN

    RST <= RESETNeg AFTER 100 ns;

    DQ_SIGNAL: PROCESS (LDQIn,UDQIn)
    BEGIN
        DQIn(7 DOWNTO 0) <= LDQIn;
        DQIn(15 DOWNTO 8) <= UDQIn;
    END PROCESS DQ_SIGNAL;

    DQS_SIGNAL: PROCESS(LDQSIn)
    BEGIN
        DQSIn <= LDQSIn;
        DQSNegIn <= NOT LDQSIn;
    END PROCESS DQS_SIGNAL;

    DQOUT_ZD_SIGNAL: PROCESS(UDQOut_zd,LDQOut_zd)
    BEGIN
        DQOut_zd <= UDQOut_zd & LDQOut_zd;
    END PROCESS DQOUT_ZD_SIGNAL;

    DQSOUT_ZD_SIGNAL: PROCESS(LDQSOut_zd)
    BEGIN
        DQSOut_zd <= LDQSOut_zd;
    END PROCESS DQSOUT_ZD_SIGNAL;

    CK_DLL: PROCESS(CKDiff)
        VARIABLE Previous   : time := 0 ns;
        VARIABLE TmpPer     : time := 0 ns;
    BEGIN
        IF rising_edge(CKDiff) THEN
            TmpPer := NOW - Previous;
            IF TmpPer > 0 ns THEN
                CKPeriod <= TmpPer;
            END IF;
            Previous := NOW;
            CKHalfPer <= CKPeriod / 2;
            CKDLLDelay <= CKPeriod + tpd_CK_LDQ1;
        END IF;
    END PROCESS CK_DLL;

    CK_temp: PROCESS(CKDiff) -- generating internal clock from DLL
    BEGIN
        CKtemp <= NOT CKtemp AFTER CKHalfPer;
    END PROCESS CK_temp;

    CKInt <= TRANSPORT CKtemp AFTER CKDLLDelay;

    Clock_init: PROCESS(CK)
    BEGIN
        IF rising_edge(CK) AND NOT PoweredUp THEN
            CK_COUNT <= CK_COUNT + 1;
        END IF;
    END PROCESS Clock_init;

    Power_up: PROCESS(CK_stable,CK_COUNT)
    BEGIN
        IF CK_stable AND (CK_COUNT >= 5) AND NOT PoweredUp THEN
            PoweredUp <= TRUE;
        END IF;
    END PROCESS Power_up;

    Init_d: PROCESS(In_d)
    BEGIN
        IF In_d THEN
            Init_delay <= TRUE AFTER tdevice_tXPR;
        ELSE
            Init_delay <= FALSE;
        END IF;
    END PROCESS Init_d;

    Init_d1: PROCESS(In_d1)
    BEGIN
        IF In_d1 THEN
            Init_delay1 <= TRUE AFTER tdevice_tMRD;
        ELSE
            Init_delay1 <= FALSE;
        END IF;
    END PROCESS Init_d1;

    Init_d2: PROCESS(In_d2)
    BEGIN
        IF In_d2 THEN
            Init_delay2 <= TRUE AFTER tdevice_tZQINIT;
        ELSE
            Init_delay2 <= FALSE;
        END IF;
    END PROCESS Init_d2;

    Init_d3: PROCESS(In_d3)
    BEGIN
        IF In_d3 THEN
            Init_delay3 <= TRUE AFTER tdevice_tZQOPER;
        ELSE
            Init_delay3 <= FALSE;
        END IF;
    END PROCESS Init_d3;

    Init_d4: PROCESS(In_d4)
    BEGIN
        IF In_d4 THEN
            Init_delay4 <= TRUE AFTER tdevice_tZQCS;
        ELSE
            Init_delay4 <= FALSE;
        END IF;
    END PROCESS Init_d4;

    PROCESS (tMOD_in_tmp)
    BEGIN
        IF rising_edge(tMOD_in_tmp) THEN
            tMOD_out_tmp <= '0', '1' AFTER tdevice_tMOD;
        END IF;
    END PROCESS;

    DLLdelay: PROCESS(DLL_delay, CKDiff)
        VARIABLE cnt : natural;
    BEGIN
        IF rising_edge(DLL_delay) THEN
            cnt := 0;
            DLL_delay_elapsed <= FALSE;
        ELSIF rising_edge(CKDiff) AND NOT DLL_delay_elapsed THEN
            cnt := cnt + 1;
            IF cnt = 511 THEN
                DLL_delay_elapsed <= TRUE;
            END IF;
        END IF;
    END PROCESS DLLdelay;

    ----------------------------------------------------------------------------
    -- Vital Behavior Process
    ----------------------------------------------------------------------------
    VITALBehaviour: PROCESS(CKDiff, DQSDiff, DQSIn, DQIn,
                            DM, ODT, CKE, CSNeg, RASNeg, CASNeg,
                            WENeg, BAIn, AIn, RESETNeg)

        -- Timing Check Variables
        VARIABLE Tviol_DQ0_DQS     : X01 := '0';
        VARIABLE TD_DQ0_DQS        : VitalTimingDataType;

        VARIABLE Tviol_DQ0_DQS1    : X01 := '0';
        VARIABLE TD_DQ0_DQS1       : VitalTimingDataType;

        VARIABLE Tviol_DQ1_DQS     : X01 := '0';
        VARIABLE TD_DQ1_DQS        : VitalTimingDataType;

        VARIABLE Tviol_DQ1_DQS1    : X01 := '0';
        VARIABLE TD_DQ1_DQS1       : VitalTimingDataType;

        VARIABLE Tviol_DM0_DQS     : X01 := '0';
        VARIABLE TD_DM0_DQS        : VitalTimingDataType;

        VARIABLE Tviol_DM0_DQS1    : X01 := '0';
        VARIABLE TD_DM0_DQS1       : VitalTimingDataType;

        VARIABLE Tviol_DM1_DQS     : X01 := '0';
        VARIABLE TD_DM1_DQS        : VitalTimingDataType;

        VARIABLE Tviol_DM1_DQS1    : X01 := '0';
        VARIABLE TD_DM1_DQS1       : VitalTimingDataType;

        VARIABLE Tviol_ODT_CK      : X01 := '0';
        VARIABLE TD_ODT_CK         : VitalTimingDataType;

        VARIABLE Tviol_CKE_CK      : X01 := '0';
        VARIABLE TD_CKE_CK         : VitalTimingDataType;

        VARIABLE Tviol_CKE_CK_RESET      : X01 := '0';
        VARIABLE TD_CKE_CK_RESET         : VitalTimingDataType;

        VARIABLE Tviol_CSNeg_CK    : X01 := '0';
        VARIABLE TD_CSNeg_CK       : VitalTimingDataType;

        VARIABLE Tviol_RASNeg_CK   : X01 := '0';
        VARIABLE TD_RASNeg_CK      : VitalTimingDataType;

        VARIABLE Tviol_CASNeg_CK   : X01 := '0';
        VARIABLE TD_CASNeg_CK      : VitalTimingDataType;

        VARIABLE Tviol_WENeg_CK    : X01 := '0';
        VARIABLE TD_WENeg_CK       : VitalTimingDataType;

        VARIABLE Tviol_BA0_CK      : X01 := '0';
        VARIABLE TD_BA0_CK         : VitalTimingDataType;

        VARIABLE Tviol_A0_CK       : X01 := '0';
        VARIABLE TD_A0_CK          : VitalTimingDataType;

        VARIABLE Tviol_DQS_CK5     : X01 := '0';
        VARIABLE TD_DQS_CK5        : VitalTimingDataType;

        VARIABLE Tviol_DQS_CK6     : X01 := '0';
        VARIABLE TD_DQS_CK6        : VitalTimingDataType;

        VARIABLE Tviol_DQS_CK7     : X01 := '0';
        VARIABLE TD_DQS_CK7        : VitalTimingDataType;

        VARIABLE Tviol_DQS_CK8     : X01 := '0';
        VARIABLE TD_DQS_CK8        : VitalTimingDataType;

        VARIABLE Tviol_DQS_CK9     : X01 := '0';
        VARIABLE TD_DQS_CK9        : VitalTimingDataType;

        VARIABLE Tviol_DQS_CK10    : X01 := '0';
        VARIABLE TD_DQS_CK10       : VitalTimingDataType;

        VARIABLE Tviol_DQS1_CK5    : X01 := '0';
        VARIABLE TD_DQS1_CK5       : VitalTimingDataType;

        VARIABLE Tviol_DQS1_CK6    : X01 := '0';
        VARIABLE TD_DQS1_CK6       : VitalTimingDataType;

        VARIABLE Tviol_DQS1_CK7    : X01 := '0';
        VARIABLE TD_DQS1_CK7       : VitalTimingDataType;

        VARIABLE Tviol_DQS1_CK8    : X01 := '0';
        VARIABLE TD_DQS1_CK8       : VitalTimingDataType;

        VARIABLE Tviol_DQS1_CK9    : X01 := '0';
        VARIABLE TD_DQS1_CK9       : VitalTimingDataType;

        VARIABLE Tviol_DQS1_CK10   : X01 := '0';
        VARIABLE TD_DQS1_CK10      : VitalTimingDataType;

        VARIABLE Tviol_CKE_RESETNeg   : X01 := '0';
        VARIABLE TD_CKE_RESETNeg      : VitalTimingDataType;

        VARIABLE Tviol_CK_DQSDiff   : X01 := '0';
        VARIABLE TD_CK_DQSDiff      : VitalTimingDataType;

        VARIABLE Tviol_CK_DQSIn   : X01 := '0';
        VARIABLE TD_CK_DQSIn      : VitalTimingDataType;

        VARIABLE Pviol_A05         : X01 := '0';
        VARIABLE PD_A05            : VitalPeriodDataType := Vi