edj1316ba.vhd

vhdl cod for ram.For sp3e

            CKE            : IN    std_ulogic := 'U';
            CSNeg          : IN    std_ulogic := 'U';
            RASNeg         : IN    std_ulogic := 'U';
            CASNeg         : IN    std_ulogic := 'U';
            WENeg          : IN    std_ulogic := 'U';
            LDM            : IN    std_ulogic := 'U';
            UDM            : IN    std_ulogic := 'U';
            RESETNeg       : IN    std_ulogic := 'U';
            BAIn           : IN    std_logic_vector(2 DOWNTO 0) :=
                                               (OTHERS => 'U');
            AIn            : IN    std_logic_vector(13 DOWNTO 0) :=
                                               (OTHERS => 'U');
            UDQIn          : IN    std_logic_vector(7 DOWNTO 0) :=
                                              (OTHERS => 'U');
            UDQOut         : OUT   std_ulogic_vector(7 DOWNTO 0) :=
                                              (OTHERS => 'Z');
            LDQIn          : IN    std_logic_vector(7 DOWNTO 0) :=
                                              (OTHERS => 'U');
            LDQOut         : OUT   std_ulogic_vector(7 DOWNTO 0) :=
                                               (OTHERS => 'Z');
            LDQSIn         : IN    std_ulogic := 'U';
            LDQSOut        : OUT   std_ulogic := 'Z';
            LDQSNegIn      : IN    std_ulogic := 'U';
            LDQSNegOut     : OUT   std_ulogic := 'Z';
            UDQSIn         : IN    std_ulogic := 'U';
            UDQSOut        : OUT   std_ulogic := 'Z';
            UDQSNegIn      : IN    std_ulogic := 'U';
            UDQSNegOut     : OUT   std_ulogic := 'Z'
        );

        PORT MAP (
            ODT       => ODT_nwv,
            CK        => CK_nwv,
            CKNeg     => CKNeg_nwv,
            CKE       => CKE_nwv,
            CSNeg     => CSNeg_nwv,
            RASNeg    => RASNeg_nwv,
            CASNeg    => CASNeg_nwv,
            WENeg     => WENeg_nwv,
            LDM        => LDM_nwv,
            UDM        => UDM_nwv,
            BAIn(0)   => BA0_nwv,
            BAIn(1)   => BA1_nwv,
            BAIn(2)   => BA2_nwv,
            AIn(0)    => A0_nwv,
            AIn(1)    => A1_nwv,
            AIn(2)    => A2_nwv,
            AIn(3)    => A3_nwv,
            AIn(4)    => A4_nwv,
            AIn(5)    => A5_nwv,
            AIn(6)    => A6_nwv,
            AIn(7)    => A7_nwv,
            AIn(8)    => A8_nwv,
            AIn(9)    => A9_nwv,
            AIn(10)   => A10_nwv,
            AIn(11)   => A11_nwv,
            AIn(12)   => A12_nwv,
            AIn(13)   => A13_nwv,
            LDQIn(0)   => LDQ0_nwv,
            LDQIn(1)   => LDQ1_nwv,
            LDQIn(2)   => LDQ2_nwv,
            LDQIn(3)   => LDQ3_nwv,
            LDQIn(4)   => LDQ4_nwv,
            LDQIn(5)   => LDQ5_nwv,
            LDQIn(6)   => LDQ6_nwv,
            LDQIn(7)   => LDQ7_nwv,
            UDQIn(0)   => UDQ0_nwv,
            UDQIn(1)   => UDQ1_nwv,
            UDQIn(2)   => UDQ2_nwv,
            UDQIn(3)   => UDQ3_nwv,
            UDQIn(4)   => UDQ4_nwv,
            UDQIn(5)   => UDQ5_nwv,
            UDQIn(6)   => UDQ6_nwv,
            UDQIn(7)   => UDQ7_nwv,
            LDQOut(0)  => LDQ0,
            LDQOut(1)  => LDQ1,
            LDQOut(2)  => LDQ2,
            LDQOut(3)  => LDQ3,
            LDQOut(4)  => LDQ4,
            LDQOut(5)  => LDQ5,
            LDQOut(6)  => LDQ6,
            LDQOut(7)  => LDQ7,
            UDQOut(0)  => UDQ0,
            UDQOut(1)  => UDQ1,
            UDQOut(2)  => UDQ2,
            UDQOut(3)  => UDQ3,
            UDQOut(4)  => UDQ4,
            UDQOut(5)  => UDQ5,
            UDQOut(6)  => UDQ6,
            UDQOut(7)  => UDQ7,
            RESETNeg  => RESETNeg_nwv,
            LDQSIn     => LDQS_nwv,
            LDQSOut    => LDQS,
            LDQSNegIn  => LDQSNeg_nwv,
            LDQSNegOut => LDQSNeg,
            UDQSIn     => UDQS_nwv,
            UDQSOut    => UDQS,
            UDQSNegIn  => UDQSNeg_nwv,
            UDQSNegOut => UDQSNeg
        );

        --zero delay signals
        SIGNAL DQIn : std_logic_vector(15 DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL DQOut_zd : std_logic_vector(15 DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL DOut_Pass : std_logic_vector(15 DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL LDQOut_zd : std_logic_vector(7 DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL UDQOut_zd : std_logic_vector(7 DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL LDQSOut_zd : std_logic := 'Z';
        SIGNAL LDQSNegOut_zd : std_logic := 'Z';
        SIGNAL UDQSOut_zd : std_logic := 'Z';
        SIGNAL UDQSNegOut_zd : std_logic := 'Z';
        SIGNAL DM : std_logic := 'Z';
        SIGNAL DQSIn : std_logic := 'Z';
        SIGNAL DQSNegIn : std_logic := 'Z';
        SIGNAL DQSOut_zd : std_logic := 'Z';
        SIGNAL DQSNegOut_zd : std_logic := 'Z';

        --differential inputs
        SIGNAL CKDiff : std_logic := 'Z';
        SIGNAL DQSDiff  : std_logic := 'Z';

        --DLL implementation
        SIGNAL CKPeriod : time := 3 ns;
        SIGNAL CKInt : std_ulogic := '0';
        SIGNAL CKtemp : std_ulogic := '1';
        SIGNAL CKHalfPer : time := 0 ns;
        SIGNAL CKDLLDelay: time := 0 ns;

        SIGNAL CK_stable : boolean := FALSE;
        SIGNAL PoweredUp : boolean := FALSE;
        SIGNAL In_d : boolean := FALSE; --delay before first MRS command tXPR
        SIGNAL In_d1 : boolean := FALSE; --mode register set comand cycle time
                                            --during initialization
        SIGNAL In_d2 : boolean := FALSE; -- delay during initial ZQ calibration
        SIGNAL In_d3 : boolean := FALSE; -- delay during reset ZQ calibration
        SIGNAL In_d4 : boolean := FALSE; -- delay during ZQ calibration
        SIGNAL Init_delay : boolean := FALSE;--command during initialization
        SIGNAL Init_delay1 : boolean := FALSE;--command during initialization
        SIGNAL Init_delay2 : boolean := FALSE;--command during initialization
        SIGNAL Init_delay3 : boolean := FALSE;--command during reset ZQ
                                                                --calibration
        SIGNAL Init_delay4 : boolean := FALSE;--command during ZQ calibration
        SIGNAL Initialized : boolean := FALSE;--initialization completed
        SIGNAL DLL_delay : std_logic := '0';       --delay between DLL
        SIGNAL DLL_delay_elapsed : boolean := TRUE;--reset and read command
        SIGNAL In_data : std_ulogic := '0';--start of write operation
        SIGNAL preamble_gen : std_logic := 'Z';--preamble before read operation
        SIGNAL Out_data : std_logic := 'Z';--start of read operation
        SIGNAL fly_flag : std_logic := '0'; --Determine weather read or write
                            -- command is BL4 or BL8 on the fly
        SIGNAL DQ_driven : boolean;-- DQ driven during Write Leveling procedure
        -- timing check violation
        SIGNAL Viol : X01 := '0';
        SIGNAL CK_COUNT : natural := 0;
        --burst sequences
        TYPE sequence IS ARRAY (0 TO 7) OF integer RANGE -7 TO 7;
        TYPE seqtab   IS ARRAY (0 TO 7) OF sequence;
        CONSTANT seq0 : sequence := (0, 1, 2, 3, 4, 5, 6, 7);
        CONSTANT seq1 : sequence := (0, 1, 2,-1, 4, 5, 6, 3);
        CONSTANT seq2 : sequence := (0, 1,-2,-1, 4, 5, 2, 3);
        CONSTANT seq3 : sequence := (0,-3,-2,-1, 4, 1, 2, 3);
        CONSTANT seq4 : sequence := (0, 1, 2, 3,-4,-3,-2,-1);
        CONSTANT seq5 : sequence := (0, 1, 2,-1,-4,-3,-2,-5);
        CONSTANT seq6 : sequence := (0, 1,-2,-1,-4,-3,-6,-5);
        CONSTANT seq7 : sequence := (0,-3,-2,-1,-4,-7,-6,-5);
        CONSTANT seq  : seqtab   := (seq0, seq1, seq2, seq3, seq4, seq5, seq6,
                                     seq7);
        CONSTANT inl0 : sequence := (0, 1, 2, 3, 4, 5, 6, 7);
        CONSTANT inl1 : sequence := (0,-1, 2, 1, 4, 3, 6, 5);
        CONSTANT inl2 : sequence := (0, 1,-2,-1, 4, 5, 2, 3);
        CONSTANT inl3 : sequence := (0,-1,-2,-3, 4, 3, 2, 1);
        CONSTANT inl4 : sequence := (0, 1, 2, 3,-4,-3,-2,-1);
        CONSTANT inl5 : sequence := (0,-1, 2, 1,-4,-5,-2,-3);
        CONSTANT inl6 : sequence := (0, 1,-2,-1,-4,-3,-6,-5);
        CONSTANT inl7 : sequence := (0,-1,-2,-3,-4,-5,-6,-7);
        CONSTANT inl  : seqtab   := (inl0, inl1, inl2, inl3, inl4, inl5, inl6,
                               inl7);

        --memory definition
        TYPE MemStore IS ARRAY (0 TO MemSize) OF integer RANGE -2 TO MaxData;
        TYPE MemBlock IS ARRAY (0 TO BankNum) OF MemStore;
        SHARED VARIABLE Mem    : MemBlock;

        --mode registers
        SHARED VARIABLE MR0 : std_logic_vector(15 DOWNTO 0) := (OTHERS => '0');
        SHARED VARIABLE MR1 : std_logic_vector(15 DOWNTO 0);
        SHARED VARIABLE MR2 : std_logic_vector(15 DOWNTO 0);
        SHARED VARIABLE MR3 : std_logic_vector(15 DOWNTO 0);

        SHARED VARIABLE burst_len : natural RANGE 4 TO 8;--burst length

        SHARED VARIABLE active_forbid : boolean := FALSE;--more than 4 active
                                                         --commands during tFAW

        --bank, row and column of scheduled read or write operation
        SHARED VARIABLE current_bank : natural RANGE 0 TO BankNum;
        SHARED VARIABLE current_row : natural RANGE 0 TO RowNum;
        SHARED VARIABLE current_column : natural RANGE 0 TO ColNum;

        --bank, row and column of read operation that starts
        SHARED VARIABLE read_bank : natural RANGE 0 TO BankNum;
        SHARED VARIABLE read_row : natural RANGE 0 TO RowNum;
        SHARED VARIABLE read_column : natural RANGE 0 TO ColNum;
        -- WRITE LEVELING PROCEDURE
        SIGNAL WL_on : boolean := FALSE;--Write Leveling enabled
        SHARED VARIABLE ODTLOFF : boolean := FALSE;

        TYPE write_sch_type IS ARRAY (0 TO 10) OF boolean;
        TYPE write_sch_bank_type IS ARRAY (0 TO BankNum) OF write_sch_type;
        --all scheduled reads within all banks
        SHARED VARIABLE read_sch : write_sch_bank_type :=
                                                  (OTHERS => (OTHERS => FALSE));
        --reads that should be preceeded by preamble
        SHARED VARIABLE preamble : write_sch_bank_type :=
                                                  (OTHERS => (OTHERS => TRUE));

        TYPE wait_read_type IS ARRAY (0 TO 10) OF std_ulogic;
        TYPE wait_read_bank_type IS ARRAY (0 TO BankNum) OF wait_read_type;
        --wait_read triggers process that counts remaining cycles to the
        --beggining of scheduled read when aditive latency has elapsed, and
        --read_delay keeps information of number of remaining cycles
        SIGNAL wait_read : wait_read_bank_type;
        SHARED VARIABLE read_delay : natural RANGE 0 TO 10;

        --needed for check if all rows were refreshed during refresh period
        SIGNAL Ref_per_start : std_ulogic := '0';
        SIGNAL Ref_per_expired : std_ulogic := '0';

        SHARED VARIABLE CK_rise : time := 0 ns;
        SHARED VARIABLE CK_period : time := 0 ns;

        TYPE Bank_state_type IS (precharged, refreshing, MRsetting, activating,
                                 active, reading, readingAP, writting,
                                 writtingAP, precharging, prechall,ZQ_calib);
        TYPE Bank_state_array_type IS ARRAY (0 TO BankNum) OF Bank_state_type;
        SHARED VARIABLE Curr_bank_state : Bank_state_array_type;
        SHARED VARIABLE Next_bank_state : Bank_state_array_type;

        SHARED VARIABLE SR_cond : boolean := FALSE;--self refresh can be entered
        SIGNAL SelfRefresh : boolean := FALSE;--self refresh active
        --Partial self refresh active
        SIGNAL PartialSelfRefresh : boolean := FALSE;
        SIGNAL SR_exit : boolean := FALSE;--CKE high, self refresh exit
        SHARED VARIABLE SR_enter_cycle : boolean := FALSE;--clock can be
                                                          --turned off

        SIGNAL Pre_PD : boolean := FALSE;--precharge power down active
        SIGNAL Act_PD : boolean := FALSE;--active power down active
        SHARED VARIABLE Read_Start : boolean := FALSE;--read burst in progress,
        SIGNAL ReadStart : boolean := FALSE;          --no pd entry

        SIGNAL Reset : boolean := FALSE;--reset function active
        SIGNAL RST              : std_logic := '1';
        SHARED VARIABLE Reset_enter_cycle : boolean := FALSE;--clocks can be
                                                             --turned off
        SIGNAL SimulationEnd : boolean := FALSE;