edj1316ba.vhd

vhdl cod for ram.For sp3e

        A12             : IN    std_ulogic := 'U';
        A13             : IN    std_ulogic := 'U';
        LDQ0            : INOUT std_ulogic := 'U';
        LDQ1            : INOUT std_ulogic := 'U';
        LDQ2            : INOUT std_ulogic := 'U';
        LDQ3            : INOUT std_ulogic := 'U';
        LDQ4            : INOUT std_ulogic := 'U';
        LDQ5            : INOUT std_ulogic := 'U';
        LDQ6            : INOUT std_ulogic := 'U';
        LDQ7            : INOUT std_ulogic := 'U';
        UDQ0            : INOUT std_ulogic := 'U';
        UDQ1            : INOUT std_ulogic := 'U';
        UDQ2            : INOUT std_ulogic := 'U';
        UDQ3            : INOUT std_ulogic := 'U';
        UDQ4            : INOUT std_ulogic := 'U';
        UDQ5            : INOUT std_ulogic := 'U';
        UDQ6            : INOUT std_ulogic := 'U';
        UDQ7            : INOUT std_ulogic := 'U';
        LDM             : IN    std_ulogic := 'U';
        UDM             : IN    std_ulogic := 'U';
        LDQS            : INOUT std_ulogic := 'U';
        LDQSNeg         : INOUT std_ulogic := 'U';
        UDQS            : INOUT std_ulogic := 'U';
        UDQSNeg         : INOUT std_ulogic := 'U';
        RESETNeg        : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 OF edj1316ba : ENTITY IS TRUE;
END edj1316ba;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral_static_memory_allocation OF edj1316ba IS
    ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral_static_memory_allocation:
    ARCHITECTURE IS TRUE;

    CONSTANT PartID         : string := "EDJ1316BA";
    CONSTANT BankNum        : natural := 7;
    CONSTANT MaxData        : natural := 16#FFFF#;
    CONSTANT MemSize        : natural := 16#7FFFFF#;
    CONSTANT RowNum         : natural := 16#1FFF#;
    CONSTANT ColNum         : natural := 16#3FF#;

    -- ipd
    SIGNAL ODT_ipd          : std_ulogic := 'U';
    SIGNAL CK_ipd           : std_ulogic := 'U';
    SIGNAL CKNeg_ipd        : std_ulogic := 'U';
    SIGNAL CKE_ipd          : std_ulogic := 'U';
    SIGNAL CSNeg_ipd        : std_ulogic := 'U';
    SIGNAL RASNeg_ipd       : std_ulogic := 'U';
    SIGNAL CASNeg_ipd       : std_ulogic := 'U';
    SIGNAL WENeg_ipd        : std_ulogic := 'U';
    SIGNAL LDM_ipd          : std_ulogic := 'U';
    SIGNAL UDM_ipd          : std_ulogic := 'U';
    SIGNAL BA0_ipd          : std_ulogic := 'U';
    SIGNAL BA1_ipd          : std_ulogic := 'U';
    SIGNAL BA2_ipd          : std_ulogic := 'U';
    SIGNAL A0_ipd           : std_ulogic := 'U';
    SIGNAL A1_ipd           : std_ulogic := 'U';
    SIGNAL A2_ipd           : std_ulogic := 'U';
    SIGNAL A3_ipd           : std_ulogic := 'U';
    SIGNAL A4_ipd           : std_ulogic := 'U';
    SIGNAL A5_ipd           : std_ulogic := 'U';
    SIGNAL A6_ipd           : std_ulogic := 'U';
    SIGNAL A7_ipd           : std_ulogic := 'U';
    SIGNAL A8_ipd           : std_ulogic := 'U';
    SIGNAL A9_ipd           : std_ulogic := 'U';
    SIGNAL A10_ipd          : std_ulogic := 'U';
    SIGNAL A11_ipd          : std_ulogic := 'U';
    SIGNAL A12_ipd          : std_ulogic := 'U';
    SIGNAL A13_ipd          : std_ulogic := 'U';
    SIGNAL LDQ0_ipd         : std_ulogic := 'U';
    SIGNAL LDQ1_ipd         : std_ulogic := 'U';
    SIGNAL LDQ2_ipd         : std_ulogic := 'U';
    SIGNAL LDQ3_ipd         : std_ulogic := 'U';
    SIGNAL LDQ4_ipd         : std_ulogic := 'U';
    SIGNAL LDQ5_ipd         : std_ulogic := 'U';
    SIGNAL LDQ6_ipd         : std_ulogic := 'U';
    SIGNAL LDQ7_ipd         : std_ulogic := 'U';
    SIGNAL UDQ0_ipd         : std_ulogic := 'U';
    SIGNAL UDQ1_ipd         : std_ulogic := 'U';
    SIGNAL UDQ2_ipd         : std_ulogic := 'U';
    SIGNAL UDQ3_ipd         : std_ulogic := 'U';
    SIGNAL UDQ4_ipd         : std_ulogic := 'U';
    SIGNAL UDQ5_ipd         : std_ulogic := 'U';
    SIGNAL UDQ6_ipd         : std_ulogic := 'U';
    SIGNAL UDQ7_ipd         : std_ulogic := 'U';
    SIGNAL LDQS_ipd         : std_ulogic := 'U';
    SIGNAL LDQSNeg_ipd      : std_ulogic := 'U';
    SIGNAL UDQS_ipd         : std_ulogic := 'U';
    SIGNAL UDQSNeg_ipd      : std_ulogic := 'U';
    SIGNAL RESETNeg_ipd     : std_ulogic := 'U';

    -- nwv
    SIGNAL ODT_nwv          : std_ulogic := 'U';
    SIGNAL CK_nwv           : std_ulogic := 'U';
    SIGNAL CKNeg_nwv        : std_ulogic := 'U';
    SIGNAL CKE_nwv          : std_ulogic := 'U';
    SIGNAL CSNeg_nwv        : std_ulogic := 'U';
    SIGNAL RASNeg_nwv       : std_ulogic := 'U';
    SIGNAL CASNeg_nwv       : std_ulogic := 'U';
    SIGNAL WENeg_nwv        : std_ulogic := 'U';
    SIGNAL BA0_nwv          : std_ulogic := 'U';
    SIGNAL BA1_nwv          : std_ulogic := 'U';
    SIGNAL BA2_nwv          : std_ulogic := 'U';
    SIGNAL A0_nwv           : std_ulogic := 'U';
    SIGNAL A1_nwv           : std_ulogic := 'U';
    SIGNAL A2_nwv           : std_ulogic := 'U';
    SIGNAL A3_nwv           : std_ulogic := 'U';
    SIGNAL A4_nwv           : std_ulogic := 'U';
    SIGNAL A5_nwv           : std_ulogic := 'U';
    SIGNAL A6_nwv           : std_ulogic := 'U';
    SIGNAL A7_nwv           : std_ulogic := 'U';
    SIGNAL A8_nwv           : std_ulogic := 'U';
    SIGNAL A9_nwv           : std_ulogic := 'U';
    SIGNAL A10_nwv          : std_ulogic := 'U';
    SIGNAL A11_nwv          : std_ulogic := 'U';
    SIGNAL A12_nwv          : std_ulogic := 'U';
    SIGNAL A13_nwv          : std_ulogic := 'U';
    SIGNAL LDQ0_nwv          : std_ulogic := 'U';
    SIGNAL LDQ1_nwv          : std_ulogic := 'U';
    SIGNAL LDQ2_nwv          : std_ulogic := 'U';
    SIGNAL LDQ3_nwv          : std_ulogic := 'U';
    SIGNAL LDQ4_nwv          : std_ulogic := 'U';
    SIGNAL LDQ5_nwv          : std_ulogic := 'U';
    SIGNAL LDQ6_nwv          : std_ulogic := 'U';
    SIGNAL LDQ7_nwv          : std_ulogic := 'U';
    SIGNAL UDQ0_nwv          : std_ulogic := 'U';
    SIGNAL UDQ1_nwv          : std_ulogic := 'U';
    SIGNAL UDQ2_nwv          : std_ulogic := 'U';
    SIGNAL UDQ3_nwv          : std_ulogic := 'U';
    SIGNAL UDQ4_nwv          : std_ulogic := 'U';
    SIGNAL UDQ5_nwv          : std_ulogic := 'U';
    SIGNAL UDQ6_nwv          : std_ulogic := 'U';
    SIGNAL UDQ7_nwv          : std_ulogic := 'U';
    SIGNAL LDM_nwv           : std_ulogic := 'U';
    SIGNAL UDM_nwv           : std_ulogic := 'U';
    SIGNAL LDQS_nwv          : std_ulogic := 'U';
    SIGNAL LDQSNeg_nwv       : std_ulogic := 'U';
    SIGNAL UDQS_nwv          : std_ulogic := 'U';
    SIGNAL UDQSNeg_nwv       : std_ulogic := 'U';
    SIGNAL RESETNeg_nwv     : std_ulogic := 'U';

    ---  internal delays
    SIGNAL tRC_in      : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1');
    SIGNAL tRC_out     : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1');
    SIGNAL tRRD_in          : std_ulogic := '1';
    SIGNAL tRRD_out         : std_ulogic := '1';
    SIGNAL tRCD_in     : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0');
    SIGNAL tRCD_out    : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0');
    SIGNAL tFAW_in          : std_ulogic_vector(3 DOWNTO 0) := (OTHERS => '0');
    SIGNAL tFAW_out         : std_ulogic_vector(3 DOWNTO 0) := (OTHERS => '0');
    SIGNAL tRASMIN_in  : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1');
    SIGNAL tRASMIN_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1');
    SIGNAL tRASMAX_in  : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0');
    SIGNAL tRASMAX_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0');
    SIGNAL tRTP_in     : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1');
    SIGNAL tRTP_out    : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1');
    SIGNAL tWR_in      : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1');
    SIGNAL tWR_out     : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1');
    SIGNAL tWTR_in     : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1');
    SIGNAL tWTR_out    : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1');
    SIGNAL tRP_in      : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0');
    SIGNAL tRP_out     : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0');
    SIGNAL tCKESR_in   : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0');
    SIGNAL tCKESR_out  : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0');
    SIGNAL tRFCMIN_in       : std_ulogic := '0';
    SIGNAL tRFCMIN_out      : std_ulogic := '0';
    SIGNAL tXS_in           : std_ulogic := '0';
    SIGNAL tXS_out          : std_ulogic := '0';
    SIGNAL tREFPer_in       : std_ulogic := '0';
    SIGNAL tREFPer_out      : std_ulogic := '0';
    SIGNAL tCKAVGMAX_in     : std_ulogic := '0';
    SIGNAL tCKAVGMAX_out    : std_ulogic := '0';
    SIGNAL tWPSTMAX_in      : std_ulogic := '0';
    SIGNAL tWPSTMAX_out     : std_ulogic := '0';
    SIGNAL tCKSRX_in        : std_ulogic := '0';
    SIGNAL tCKSRX_out       : std_ulogic := '0';
    SIGNAL tCKSRE_in        : std_ulogic := '0';
    SIGNAL tCKSRE_out       : std_ulogic := '0';
    SIGNAL tWLDQSEN_in      : std_ulogic := '0';
    SIGNAL tWLDQSEN_out     : std_ulogic := '0';
    SIGNAL tWLODTEN_in      : std_ulogic := '0';
    SIGNAL tWLODTEN_out     : std_ulogic := '0';
    SIGNAL tWLMRD_in        : std_ulogic := '0';
    SIGNAL tWLMRD_out       : std_ulogic := '0';
    SIGNAL tWLOMAX_in       : std_ulogic := '0';
    SIGNAL tWLOMAX_out      : std_ulogic := '0';
    SIGNAL tWLOEMAX_in      : std_ulogic := '0';
    SIGNAL tWLOEMAX_out     : std_ulogic := '0';
    SIGNAL tODTLOFF_in      : std_ulogic := '0';
    SIGNAL tODTLOFF_out     : std_ulogic := '0';
    SIGNAL tMRD_in          : std_ulogic := '0';
    SIGNAL tMRD_out         : std_ulogic := '0';
    SIGNAL tMOD_in          : std_ulogic := '0';
    SIGNAL tMOD_out         : std_ulogic := '0';
    SIGNAL tMOD_in_tmp      : std_ulogic := '0';
    SIGNAL tMOD_out_tmp     : std_ulogic := '0';
    SIGNAL tXPR_in          : std_ulogic := '0';
    SIGNAL tXPR_out         : std_ulogic := '0';
    SIGNAL tZQINIT_in       : std_ulogic := '0';
    SIGNAL tZQINIT_out      : std_ulogic := '0';
    SIGNAL tZQOPER_in       : std_ulogic := '0';
    SIGNAL tZQOPER_out      : std_ulogic := '0';
    SIGNAL tZQCS_in         : std_ulogic := '0';
    SIGNAL tZQCS_out        : std_ulogic := '0';

BEGIN

    ----------------------------------------------------------------------------
    -- Internal Delays
    ----------------------------------------------------------------------------
    TRC      : VitalBuf(tRC_out(0),  tRC_in(0),  (tdevice_tRC - 1 ns,
                                                                    UnitDelay));
    TRC1     : VitalBuf(tRC_out(1),  tRC_in(1),  (tdevice_tRC - 1 ns,
                                                                    UnitDelay));
    TRC2     : VitalBuf(tRC_out(2),  tRC_in(2),  (tdevice_tRC - 1 ns,
                                                                    UnitDelay));
    TRC3     : VitalBuf(tRC_out(3),  tRC_in(3),  (tdevice_tRC - 1 ns,
                                                                    UnitDelay));
    TRC4     : VitalBuf(tRC_out(4),  tRC_in(4),  (tdevice_tRC - 1 ns,
                                                                    UnitDelay));
    TRC5     : VitalBuf(tRC_out(5),  tRC_in(5),  (tdevice_tRC - 1 ns,
                                                                    UnitDelay));
    TRC6     : VitalBuf(tRC_out(6),  tRC_in(6),  (tdevice_tRC - 1 ns,
                                                                    UnitDelay));
    TRC7     : VitalBuf(tRC_out(7),  tRC_in(7),  (tdevice_tRC - 1 ns,
                                                                    UnitDelay));
    TRRD     : VitalBuf(tRRD_out,    tRRD_in,    (tdevice_tRRD - 1 ns,
                                                                    UnitDelay));
    TRCD     : VitalBuf(tRCD_out(0), tRCD_in(0), (tdevice_tRCD - 1 ns,
                                                                    UnitDelay));
    TRCD1    : VitalBuf(tRCD_out(1), tRCD_in(1), (tdevice_tRCD - 1 ns,
                                                                    UnitDelay));
    TRCD2    : VitalBuf(tRCD_out(2), tRCD_in(2), (tdevice_tRCD - 1 ns,
                                                                    UnitDelay));
    TRCD3    : VitalBuf(tRCD_out(3), tRCD_in(3), (tdevice_tRCD - 1 ns,
                                                                    UnitDelay));
    TRCD4    : VitalBuf(tRCD_out(4), tRCD_in(4), (tdevice_tRCD - 1 ns,
                                                                    UnitDelay));
    TRCD5    : VitalBuf(tRCD_out(5), tRCD_in(5), (tdevice_tRCD - 1 ns,
                                                                    UnitDelay));
    TRCD6    : VitalBuf(tRCD_out(6), tRCD_in(6), (tdevice_tRCD - 1 ns,
                                                                    UnitDelay));
    TRCD7    : VitalBuf(tRCD_out(7), tRCD_in(7), (tdevice_tRCD - 1 ns,
                                                                    UnitDelay));
    TFAW     : VitalBuf(tFAW_out(0), tFAW_in(0), (tdevice_tFAW - 2 ns,
                                                                    UnitDelay));
    TFAW1    : VitalBuf(tFAW_out(1), tFAW_in(1), (tdevice_tFAW - 2 ns,
                                                                    UnitDelay));
    TFAW2    : VitalBuf(tFAW_out(2), tFAW_in(2), (tdevice_tFAW - 2 ns,
                                                                    UnitDelay));
    TFAW3    : VitalBuf(tFAW_out(3), tFAW_in(3), (tdevice_tFAW - 2 ns,
                                                                    UnitDelay));
    TRASMIN  : VitalBuf(tRASMIN_out(0), tRASMIN_in(0), (tdevice_tRASMIN - 1 ns,
                                                                    UnitDelay));
    TRASMIN1 : VitalBuf(tRASMIN_out(1), tRASMIN_in(1), (tdevice_tRASMIN - 1 ns,