📄 idt71v256.ftm

📁 vhdl cod for ram.For sp3e
💻 FTM
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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for idt71v256 Parts</TITLE><BODY><REVISION.HISTORY>version: |  author:  | mod date: | changes made:  V1.0    R. Munden    04 MAY 01   Initial release</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>idt71V256<FMFTIME>IDT71V256SA10PZ<SOURCE>Integrated Device Technology DSC-3101/07 June 2002</SOURCE>IDT71V256SA10Y<SOURCE>Integrated Device Technology DSC-3101/07 June 2002</SOURCE><COMMENT>Values are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH OENeg D0 () () (2:4:6) (3:5:6) (2:4:6) (3:5:6))    (IOPATH CENeg D0 () () (0:4:8) (5:8:10) (0:4:8) (5:8:10))    (IOPATH A0 D0 (3:6:10) (3:6:10))  ))  (TIMINGCHECK    (SETUP D0 WENeg (6))    (SETUP D0 CENeg (6))    (HOLD D0 WENeg (0))    (HOLD D0 CENeg (0))    (WIDTH (negedge WENeg) (9))  )</TIMING></FMFTIME><FMFTIME>IDT71V256SA12PZ<SOURCE>Integrated Device Technology DSC-3101/07 June 2002</SOURCE>IDT71V256SA12Y<SOURCE>Integrated Device Technology DSC-3101/07 June 2002</SOURCE><COMMENT>Values are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH OENeg D0 () () (2:4:6) (3:5:6) (2:4:6) (3:5:6))    (IOPATH CENeg D0 () () (0:4:6) (5:9:12) (0:4:6) (5:9:12))    (IOPATH A0 D0 (4:8:12) (4:8:12))  ))  (TIMINGCHECK    (SETUP D0 WENeg (6))    (SETUP D0 CENeg (6))    (HOLD D0 WENeg (0))    (HOLD D0 CENeg (0))    (WIDTH (negedge WENeg) (9))  )</TIMING></FMFTIME><FMFTIME>IDT71V256SA15PZ<SOURCE>Integrated Device Technology DSC-3101/07 June 2002</SOURCE>IDT71V256SA15Y<SOURCE>Integrated Device Technology DSC-3101/07 June 2002</SOURCE><COMMENT>Values are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH OENeg D0 () () (0:4:7) (0:4:7) (0:4:7) (0:4:7))    (IOPATH CENeg D0 () () (0:5:9) (5:10:15) (0:5:9) (5:10:15))    (IOPATH A0 D0 (5:10:15) (5:10:15))  ))  (TIMINGCHECK    (SETUP D0 WENeg (7))    (SETUP D0 CENeg (7))    (HOLD D0 WENeg (0))    (HOLD D0 CENeg (0))    (WIDTH (negedge WENeg) (10))  )</TIMING></FMFTIME><FMFTIME>IDT71V256SA20PZ<SOURCE>Integrated Device Technology DSC-3101/07 June 2002</SOURCE>IDT71V256SA20Y<SOURCE>Integrated Device Technology DSC-3101/07 June 2002</SOURCE><COMMENT>Values are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH OENeg D0 () () (0:5:8) (0:5:8) (0:5:8) (0:5:8))    (IOPATH CENeg D0 () () (0:7:10) (5:14:20) (0:7:10) (5:14:20))    (IOPATH A0 D0 (7:14:20) (7:14:20))  ))  (TIMINGCHECK    (SETUP D0 WENeg (8))    (SETUP D0 CENeg (8))    (HOLD D0 WENeg (0))    (HOLD D0 CENeg (0))    (WIDTH (negedge WENeg) (15))  )</TIMING></FMFTIME></BODY></FTML>
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