idt71v65603.vhd

vhdl cod for ram.For sp3e

    SIGNAL ZZ_ipd              : std_ulogic := 'U';
    SIGNAL LBONeg_ipd          : std_ulogic := '1';
    SIGNAL OENeg_ipd           : std_ulogic := 'U';

    SIGNAL A0_nwv              : UX01  := 'U';
    SIGNAL A1_nwv              : UX01  := 'U';
    SIGNAL A2_nwv              : UX01  := 'U';
    SIGNAL A3_nwv              : UX01  := 'U';
    SIGNAL A4_nwv              : UX01  := 'U';
    SIGNAL A5_nwv              : UX01  := 'U';
    SIGNAL A6_nwv              : UX01  := 'U';
    SIGNAL A7_nwv              : UX01  := 'U';
    SIGNAL A8_nwv              : UX01  := 'U';
    SIGNAL A9_nwv              : UX01  := 'U';
    SIGNAL A10_nwv             : UX01  := 'U';
    SIGNAL A11_nwv             : UX01  := 'U';
    SIGNAL A12_nwv             : UX01  := 'U';
    SIGNAL A13_nwv             : UX01  := 'U';
    SIGNAL A14_nwv             : UX01  := 'U';
    SIGNAL A15_nwv             : UX01  := 'U';
    SIGNAL A16_nwv             : UX01  := 'U';
    SIGNAL A17_nwv             : UX01  := 'U';
    SIGNAL DQA0_nwv            : UX01  := 'U';
    SIGNAL DQA1_nwv            : UX01  := 'U';
    SIGNAL DQA2_nwv            : UX01  := 'U';
    SIGNAL DQA3_nwv            : UX01  := 'U';
    SIGNAL DQA4_nwv            : UX01  := 'U';
    SIGNAL DQA5_nwv            : UX01  := 'U';
    SIGNAL DQA6_nwv            : UX01  := 'U';
    SIGNAL DQA7_nwv            : UX01  := 'U';
    SIGNAL DQA8_nwv            : UX01  := 'U';
    SIGNAL DQB0_nwv            : UX01  := 'U';
    SIGNAL DQB1_nwv            : UX01  := 'U';
    SIGNAL DQB2_nwv            : UX01  := 'U';
    SIGNAL DQB3_nwv            : UX01  := 'U';
    SIGNAL DQB4_nwv            : UX01  := 'U';
    SIGNAL DQB5_nwv            : UX01  := 'U';
    SIGNAL DQB6_nwv            : UX01  := 'U';
    SIGNAL DQB7_nwv            : UX01  := 'U';
    SIGNAL DQB8_nwv            : UX01  := 'U';
    SIGNAL DQC0_nwv            : UX01  := 'U';
    SIGNAL DQC1_nwv            : UX01  := 'U';
    SIGNAL DQC2_nwv            : UX01  := 'U';
    SIGNAL DQC3_nwv            : UX01  := 'U';
    SIGNAL DQC4_nwv            : UX01  := 'U';
    SIGNAL DQC5_nwv            : UX01  := 'U';
    SIGNAL DQC6_nwv            : UX01  := 'U';
    SIGNAL DQC7_nwv            : UX01  := 'U';
    SIGNAL DQC8_nwv            : UX01  := 'U';
    SIGNAL DQD0_nwv            : UX01  := 'U';
    SIGNAL DQD1_nwv            : UX01  := 'U';
    SIGNAL DQD2_nwv            : UX01  := 'U';
    SIGNAL DQD3_nwv            : UX01  := 'U';
    SIGNAL DQD4_nwv            : UX01  := 'U';
    SIGNAL DQD5_nwv            : UX01  := 'U';
    SIGNAL DQD6_nwv            : UX01  := 'U';
    SIGNAL DQD7_nwv            : UX01  := 'U';
    SIGNAL DQD8_nwv            : UX01  := 'U';
    SIGNAL ADV_nwv             : std_ulogic := 'U';
    SIGNAL R_nwv               : std_ulogic := 'U';
    SIGNAL CLKENNeg_nwv        : std_ulogic := 'U';
    SIGNAL BWDNeg_nwv          : std_ulogic := 'U';
    SIGNAL BWCNeg_nwv          : std_ulogic := 'U';
    SIGNAL BWBNeg_nwv          : std_ulogic := 'U';
    SIGNAL BWANeg_nwv          : std_ulogic := 'U';
    SIGNAL CE1Neg_nwv          : std_ulogic := 'U';
    SIGNAL CE2Neg_nwv          : std_ulogic := 'U';
    SIGNAL CE2_nwv             : std_ulogic := 'U';
    SIGNAL CLK_nwv             : std_ulogic := 'U';
    SIGNAL ZZ_nwv              : std_ulogic := 'U';
    SIGNAL LBONeg_nwv          : std_ulogic := '1';
    SIGNAL OENeg_nwv           : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_2 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_3 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_4 : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_5 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_6 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_7 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_8 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_9 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_10 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_11 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_12 : VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_13 : VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_14 : VitalWireDelay (A13_ipd, A13, tipd_A13);
        w_15 : VitalWireDelay (A14_ipd, A14, tipd_A14);
        w_16 : VitalWireDelay (A15_ipd, A15, tipd_A15);
        w_17 : VitalWireDelay (A16_ipd, A16, tipd_A16);
        w_18 : VitalWireDelay (A17_ipd, A17, tipd_A17);
        w_21 : VitalWireDelay (DQA0_ipd, DQA0, tipd_DQA0);
        w_22 : VitalWireDelay (DQA1_ipd, DQA1, tipd_DQA1);
        w_23 : VitalWireDelay (DQA2_ipd, DQA2, tipd_DQA2);
        w_24 : VitalWireDelay (DQA3_ipd, DQA3, tipd_DQA3);
        w_25 : VitalWireDelay (DQA4_ipd, DQA4, tipd_DQA4);
        w_26 : VitalWireDelay (DQA5_ipd, DQA5, tipd_DQA5);
        w_27 : VitalWireDelay (DQA6_ipd, DQA6, tipd_DQA6);
        w_28 : VitalWireDelay (DQA7_ipd, DQA7, tipd_DQA7);
        w_29 : VitalWireDelay (DQA8_ipd, DQA8, tipd_DQA8);
        w_31 : VitalWireDelay (DQB0_ipd, DQB0, tipd_DQB0);
        w_32 : VitalWireDelay (DQB1_ipd, DQB1, tipd_DQB1);
        w_33 : VitalWireDelay (DQB2_ipd, DQB2, tipd_DQB2);
        w_34 : VitalWireDelay (DQB3_ipd, DQB3, tipd_DQB3);
        w_35 : VitalWireDelay (DQB4_ipd, DQB4, tipd_DQB4);
        w_36 : VitalWireDelay (DQB5_ipd, DQB5, tipd_DQB5);
        w_37 : VitalWireDelay (DQB6_ipd, DQB6, tipd_DQB6);
        w_38 : VitalWireDelay (DQB7_ipd, DQB7, tipd_DQB7);
        w_39 : VitalWireDelay (DQB8_ipd, DQB8, tipd_DQB8);
        w_41 : VitalWireDelay (DQC0_ipd, DQC0, tipd_DQC0);
        w_42 : VitalWireDelay (DQC1_ipd, DQC1, tipd_DQC1);
        w_43 : VitalWireDelay (DQC2_ipd, DQC2, tipd_DQC2);
        w_44 : VitalWireDelay (DQC3_ipd, DQC3, tipd_DQC3);
        w_45 : VitalWireDelay (DQC4_ipd, DQC4, tipd_DQC4);
        w_46 : VitalWireDelay (DQC5_ipd, DQC5, tipd_DQC5);
        w_47 : VitalWireDelay (DQC6_ipd, DQC6, tipd_DQC6);
        w_48 : VitalWireDelay (DQC7_ipd, DQC7, tipd_DQC7);
        w_49 : VitalWireDelay (DQC8_ipd, DQC8, tipd_DQC8);
        w_51 : VitalWireDelay (DQD0_ipd, DQD0, tipd_DQD0);
        w_52 : VitalWireDelay (DQD1_ipd, DQD1, tipd_DQD1);
        w_53 : VitalWireDelay (DQD2_ipd, DQD2, tipd_DQD2);
        w_54 : VitalWireDelay (DQD3_ipd, DQD3, tipd_DQD3);
        w_55 : VitalWireDelay (DQD4_ipd, DQD4, tipd_DQD4);
        w_56 : VitalWireDelay (DQD5_ipd, DQD5, tipd_DQD5);
        w_57 : VitalWireDelay (DQD6_ipd, DQD6, tipd_DQD6);
        w_58 : VitalWireDelay (DQD7_ipd, DQD7, tipd_DQD7);
        w_59 : VitalWireDelay (DQD8_ipd, DQD8, tipd_DQD8);
        w_61 : VitalWireDelay (ADV_ipd, ADV, tipd_ADV);
        w_62 : VitalWireDelay (R_ipd, R, tipd_R);
        w_63 : VitalWireDelay (CLKENNeg_ipd, CLKENNeg, tipd_CLKENNeg);
        w_64 : VitalWireDelay (BWDNeg_ipd, BWDNeg, tipd_BWDNeg);
        w_65 : VitalWireDelay (BWCNeg_ipd, BWCNeg, tipd_BWCNeg);
        w_66 : VitalWireDelay (BWBNeg_ipd, BWBNeg, tipd_BWBNeg);
        w_67 : VitalWireDelay (BWANeg_ipd, BWANeg, tipd_BWANeg);
        w_68 : VitalWireDelay (CE1Neg_ipd, CE1Neg, tipd_CE1Neg);
        w_69 : VitalWireDelay (CE2Neg_ipd, CE2Neg, tipd_CE2Neg);
        w_70 : VitalWireDelay (CE2_ipd, CE2, tipd_CE2);
        w_71 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_72 : VitalWireDelay (ZZ_ipd, ZZ, tipd_ZZ);
        w_73 : VitalWireDelay (LBONeg_ipd, LBONeg, tipd_LBONeg);
        w_74 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);

    END BLOCK;

    A0_nwv <= To_UX01(A0_ipd);
    A1_nwv <= To_UX01(A1_ipd);
    A2_nwv <= To_UX01(A2_ipd);
    A3_nwv <= To_UX01(A3_ipd);
    A4_nwv <= To_UX01(A4_ipd);
    A5_nwv <= To_UX01(A5_ipd);
    A6_nwv <= To_UX01(A6_ipd);
    A7_nwv <= To_UX01(A7_ipd);
    A8_nwv <= To_UX01(A8_ipd);
    A9_nwv <= To_UX01(A9_ipd);
    A10_nwv <= To_UX01(A10_ipd);
    A11_nwv <= To_UX01(A11_ipd);
    A12_nwv <= To_UX01(A12_ipd);
    A13_nwv <= To_UX01(A13_ipd);
    A14_nwv <= To_UX01(A14_ipd);
    A15_nwv <= To_UX01(A15_ipd);
    A16_nwv <= To_UX01(A16_ipd);
    A17_nwv <= To_UX01(A17_ipd);
    DQA0_nwv <= To_UX01(DQA0_ipd);
    DQA1_nwv <= To_UX01(DQA1_ipd);
    DQA2_nwv <= To_UX01(DQA2_ipd);
    DQA3_nwv <= To_UX01(DQA3_ipd);
    DQA4_nwv <= To_UX01(DQA4_ipd);
    DQA5_nwv <= To_UX01(DQA5_ipd);
    DQA6_nwv <= To_UX01(DQA6_ipd);
    DQA7_nwv <= To_UX01(DQA7_ipd);
    DQA8_nwv <= To_UX01(DQA8_ipd);
    DQB0_nwv <= To_UX01(DQB0_ipd);
    DQB1_nwv <= To_UX01(DQB1_ipd);
    DQB2_nwv <= To_UX01(DQB2_ipd);
    DQB3_nwv <= To_UX01(DQB3_ipd);
    DQB4_nwv <= To_UX01(DQB4_ipd);
    DQB5_nwv <= To_UX01(DQB5_ipd);
    DQB6_nwv <= To_UX01(DQB6_ipd);
    DQB7_nwv <= To_UX01(DQB7_ipd);
    DQB8_nwv <= To_UX01(DQB8_ipd);
    DQC0_nwv <= To_UX01(DQC0_ipd);
    DQC1_nwv <= To_UX01(DQC1_ipd);
    DQC2_nwv <= To_UX01(DQC2_ipd);
    DQC3_nwv <= To_UX01(DQC3_ipd);
    DQC4_nwv <= To_UX01(DQC4_ipd);
    DQC5_nwv <= To_UX01(DQC5_ipd);
    DQC6_nwv <= To_UX01(DQC6_ipd);
    DQC7_nwv <= To_UX01(DQC7_ipd);
    DQC8_nwv <= To_UX01(DQC8_ipd);
    DQD0_nwv <= To_UX01(DQD0_ipd);
    DQD1_nwv <= To_UX01(DQD1_ipd);
    DQD2_nwv <= To_UX01(DQD2_ipd);
    DQD3_nwv <= To_UX01(DQD3_ipd);
    DQD4_nwv <= To_UX01(DQD4_ipd);
    DQD5_nwv <= To_UX01(DQD5_ipd);
    DQD6_nwv <= To_UX01(DQD6_ipd);
    DQD7_nwv <= To_UX01(DQD7_ipd);
    DQD8_nwv <= To_UX01(DQD8_ipd);
    ADV_nwv <= To_UX01(ADV_ipd);
    R_nwv <= To_UX01(R_ipd);
    CLKENNeg_nwv <= To_UX01(CLKENNeg_ipd);
    BWDNeg_nwv <= To_UX01(BWDNeg_ipd);
    BWCNeg_nwv <= To_UX01(BWCNeg_ipd);
    BWBNeg_nwv <= To_UX01(BWBNeg_ipd);
    BWANeg_nwv <= To_UX01(BWANeg_ipd);
    CE1Neg_nwv <= To_UX01(CE1Neg_ipd);
    CE2Neg_nwv <= To_UX01(CE2Neg_ipd);
    CE2_nwv <= To_UX01(CE2_ipd);
    CLK_nwv <= To_UX01(CLK_ipd);
    ZZ_nwv <= To_UX01(ZZ_ipd);
    LBONeg_nwv <= To_UX01(LBONeg_ipd);
    OENeg_nwv <= To_UX01(OENeg_ipd);

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            BWDNIn          : IN    std_ulogic := 'U';
            BWCNIn          : IN    std_ulogic := 'U';
            BWBNIn          : IN    std_ulogic := 'U';
            BWANIn          : IN    std_ulogic := 'U';
            DatDIn          : IN    std_logic_vector(8 downto 0);
            DatCIn          : IN    std_logic_vector(8 downto 0);
            DatBIn          : IN    std_logic_vector(8 downto 0);
            DatAIn          : IN    std_logic_vector(8 downto 0);
            DataOut         : OUT   std_logic_vector(35 downto 0)
                                                     := (others => 'Z');
            CLKIn           : IN    std_ulogic := 'U';
            CKENIn          : IN    std_ulogic := 'U';
            AddressIn       : IN    std_logic_vector(17 downto 0);
            OENegIn         : IN    std_ulogic := 'U';
            RIn             : IN    std_ulogic := 'U';
            ADVIn           : IN    std_ulogic := 'U';
            CE2In           : IN    std_ulogic := 'U';
            ZZIn            : IN    std_ulogic := 'U';
            LBONegIn        : IN    std_ulogic := '1';
            CE1NegIn        : IN    std_ulogic := 'U';
            CE2NegIn        : IN    std_ulogic := 'U'
        );
        PORT MAP (
            BWDNIn => BWDNeg_nwv,
            BWCNIn => BWCNeg_nwv,
            BWBNIn => BWBNeg_nwv,
            BWANIn => BWANeg_nwv,
            CLKIn => CLK_nwv,
            ZZIn => ZZ_nwv,
            CKENIn => CLKENNeg_nwv,
            OENegIn => OENeg_nwv,
            RIn => R_nwv,
            ADVIn => ADV_nwv,
            CE2In => CE2_nwv,
            LBONegIn => LBONeg_nwv,
            CE1NegIn => CE1Neg_nwv,
            CE2NegIn => CE2Neg_nwv,
            DataOut(0) =>  DQA0,
            DataOut(1) =>  DQA1,
            DataOut(2) =>  DQA2,
            DataOut(3) =>  DQA3,
            DataOut(4) =>  DQA4,
            DataOut(5) =>  DQA5,
            DataOut(6) =>  DQA6,
            DataOut(7) =>  DQA7,
            DataOut(8) =>  DQA8,
            DataOut(9) =>  DQB0,
            DataOut(10) =>  DQB1,
            DataOut(11) =>  DQB2,
            DataOut(12) =>  DQB3,
            DataOut(13) =>  DQB4,
            DataOut(14) =>  DQB5,
            DataOut(15) =>  DQB6,
            DataOut(16) =>  DQB7,
            DataOut(17) =>  DQB8,
            DataOut(18) =>  DQC0,
            DataOut(19) =>  DQC1,
            DataOut(20) =>  DQC2,