hyb18t1g160af_120.vhd

vhdl cod for ram.For sp3e

    DQ0_nwv             <= To_UX01(s => DQ0_ipd);
    DQ1_nwv             <= To_UX01(s => DQ1_ipd);
    DQ2_nwv             <= To_UX01(s => DQ2_ipd);
    DQ3_nwv             <= To_UX01(s => DQ3_ipd);
    DQ4_nwv             <= To_UX01(s => DQ4_ipd);
    DQ5_nwv             <= To_UX01(s => DQ5_ipd);
    DQ6_nwv             <= To_UX01(s => DQ6_ipd);
    DQ7_nwv             <= To_UX01(s => DQ7_ipd);
    DQ8_nwv             <= To_UX01(s => DQ8_ipd);
    DQ9_nwv             <= To_UX01(s => DQ9_ipd);
    DQ10_nwv            <= To_UX01(s => DQ10_ipd);
    DQ11_nwv            <= To_UX01(s => DQ11_ipd);
    DQ12_nwv            <= To_UX01(s => DQ12_ipd);
    DQ13_nwv            <= To_UX01(s => DQ13_ipd);
    DQ14_nwv            <= To_UX01(s => DQ14_ipd);
    DQ15_nwv            <= To_UX01(s => DQ15_ipd);
    UDQS_nwv            <= To_UX01(s => UDQS_ipd);
    UDQSNeg_nwv         <= To_UX01(s => UDQSNeg_ipd);
    LDQS_nwv            <= To_UX01(s => LDQS_ipd);
    LDQSNeg_nwv         <= To_UX01(s => LDQSNeg_ipd);
    UDM_nwv             <= To_UX01(s => UDM_ipd);
    LDM_nwv             <= To_UX01(s => LDM_ipd);

    ----------------------------------------------------------------------------
    --  Main behavior Block
    ----------------------------------------------------------------------------

    VitalBehavior: BLOCK
        PORT (
            CKIn            : IN    std_ulogic := 'U';
            CKNegIn         : IN    std_ulogic := 'U';
            CKEIn           : IN    std_ulogic := 'U';

            WENegIn         : IN    std_ulogic := 'U';
            RASNegIn        : IN    std_ulogic := 'U';
            CSNegIn         : IN    std_ulogic := 'U';
            CASNegIn        : IN    std_ulogic := 'U';

            BAIn            : IN    std_logic_vector(HiBankBit downto 0);
            AddressIn       : IN    std_logic_vector(HiAddrBit downto 0);
            DataIn          : IN    std_logic_vector(HiDataBit downto 0);
            DataOut         : OUT   std_logic_vector(HiDataBit downto 0)
                                                     := (others => 'Z');

            UDQSIn          : IN    std_logic ;
            UDQSNegIn       : IN    std_logic ;
            UDQSOut         : OUT   std_logic := 'Z';
            UDQSNegOut      : OUT   std_logic := 'Z';
            LDQSIn          : IN    std_logic := 'Z';
            LDQSNegIn       : IN    std_logic := 'Z';
            LDQSOut         : OUT   std_logic := 'Z';
            LDQSNegOut      : OUT   std_logic := 'Z';

            UDMIn           : IN    std_ulogic := 'U';
            LDMIn           : IN    std_ulogic := 'U'
        );

        PORT MAP (
            CKIn     => CK_nwv,
            CKNegIn  => CKNeg_nwv,
            CKEIn    => CKE_nwv,

            WENegIn  => WENeg_nwv,
            RASNegIn => RASNeg_nwv,
            CSNegIn  => CSNeg_nwv,
            CASNegIn => CASNeg_nwv,

            BAIn(0)  => BA0_nwv,
            BAIn(1)  => BA1_nwv,
            BAIn(2)  => BA2_nwv,

            AddressIn(0)  => A0_nwv,
            AddressIn(1)  => A1_nwv,
            AddressIn(2)  => A2_nwv,
            AddressIn(3)  => A3_nwv,
            AddressIn(4)  => A4_nwv,
            AddressIn(5)  => A5_nwv,
            AddressIn(6)  => A6_nwv,
            AddressIn(7)  => A7_nwv,
            AddressIn(8)  => A8_nwv,
            AddressIn(9)  => A9_nwv,
            AddressIn(10) => A10_nwv,
            AddressIn(11) => A11_nwv,
            AddressIn(12) => A12_nwv,

            DataIn(0)     =>  DQ0_ipd,--_nwv,
            DataIn(1)     =>  DQ1_ipd,--_nwv,
            DataIn(2)     =>  DQ2_ipd,--_nwv,
            DataIn(3)     =>  DQ3_ipd,--_nwv,
            DataIn(4)     =>  DQ4_ipd,--_nwv,
            DataIn(5)     =>  DQ5_ipd,--_nwv,
            DataIn(6)     =>  DQ6_ipd,--_nwv,
            DataIn(7)     =>  DQ7_ipd,--_nwv,
            DataIn(8)     =>  DQ8_ipd,--_nwv,
            DataIn(9)     =>  DQ9_ipd,--_nwv,
            DataIn(10)    =>  DQ10_ipd,--_nwv,
            DataIn(11)    =>  DQ11_ipd,--_nwv,
            DataIn(12)    =>  DQ12_ipd,--_nwv,
            DataIn(13)    =>  DQ13_ipd,--_nwv,
            DataIn(14)    =>  DQ14_ipd,--_nwv,
            DataIn(15)    =>  DQ15_ipd,--_nwv,

            DataOut(0)    =>  DQ0,
            DataOut(1)    =>  DQ1,
            DataOut(2)    =>  DQ2,
            DataOut(3)    =>  DQ3,
            DataOut(4)    =>  DQ4,
            DataOut(5)    =>  DQ5,
            DataOut(6)    =>  DQ6,
            DataOut(7)    =>  DQ7,
            DataOut(8)    =>  DQ8,
            DataOut(9)    =>  DQ9,
            DataOut(10)   =>  DQ10,
            DataOut(11)   =>  DQ11,
            DataOut(12)   =>  DQ12,
            DataOut(13)   =>  DQ13,
            DataOut(14)   =>  DQ14,
            DataOut(15)   =>  DQ15,

            UDQSIn   => UDQS_nwv,
            UDQSNegIn=> UDQSNeg_ipd,
            LDQSIn   => LDQS_nwv,
            LDQSNegIn=> LDQSNeg_nwv,

            UDQSOut  => UDQS,
            UDQSNegOut  => UDQSNeg,
            LDQSOut  => LDQS,
            LDQSNegOut  => LDQSNeg,

            UDMIn     => UDM_nwv,
            LDMIn     => LDM_nwv
        );

        -- Type definition for commands
        TYPE command_type is (nop,
                              deselect,
                              mrs,
                              autoref,
                              bankact,
                              presingle,
                              preall,
                              write,
                              writeapre,
                              read,
                              readapre,
                              selfrefentry,
                              pwrdwnentry,
                              selfrefpwrdwnexit
        );

        -- Type definition for state machine
        TYPE state_type IS (init_state,
                            idle_state,
                            mrs_set_state,
                            self_refresh_state,
                            auto_refresh_state,
                            pwrdown_precharge_state,
                            pwrdown_active_state,
                            activating_state,
                            bank_active_state,
                            write_state,
                            write_auto_precharge_state,
                            read_state,
                            read_auto_precharge_state,
                            precharge_state
        );

        TYPE statebanktype IS array (MaxBank-1 downto 0) of state_type;
        TYPE rowbanktype   IS array (MaxBank-1 downto 0) of INTEGER
                                                    RANGE 0 to MaxRow-1;

        TYPE burst_addr_seq_type IS (sequential, interleaved);
        TYPE power_down_mode_type IS (standard,lowpower);

        TYPE bool_array_type IS ARRAY (0 TO MaxBank-1) OF BOOLEAN;

        TYPE columnarraytype IS ARRAY (0 TO 7) OF INTEGER
                                                RANGE 0 TO MaxColumn - 1;

        TYPE burst_sequence_type IS ARRAY (0 TO 7) OF INTEGER RANGE 0 TO 15;
        TYPE sequence_4 IS ARRAY (0 TO 3) OF burst_sequence_type;
        TYPE sequence_8 IS ARRAY (0 TO 7) OF burst_sequence_type;

        SHARED VARIABLE burst_sequence : burst_sequence_type:=(0&0&0&0&0&0&0&0);
        SHARED VARIABLE burst_index   : INTEGER := 0;
        SHARED VARIABLE burst_offset  : INTEGER := 0;

        CONSTANT sa_4 : sequence_4 := ((4&5&6&7&0&0&0&0),
                                       (4&5&6&3&0&0&0&0),
                                       (4&5&2&3&0&0&0&0),
                                       (4&1&2&3&0&0&0&0));

        CONSTANT ia_4 : sequence_4 :=  ((4&5&6&7&0&0&0&0),
                                       (4&3&6&5&0&0&0&0),
                                       (4&5&2&3&0&0&0&0),
                                       (4&3&2&1&0&0&0&0));

        CONSTANT sa_8 : sequence_8 :=  ((8&9&10&11&12&13&14&15),
                                       (8&9&10&7&12&13&14&11),
                                       (8&9&6&7&12&13&10&11),
                                       (8&5&6&7&12&9&10&11),
                                       (8&9&10&11&4&5&6&7),
                                       (8&9&10&7&4&5&6&3),
                                       (8&9&6&7&4&5&2&3),
                                       (8&5&6&7&4&1&2&3));

        CONSTANT ia_8 : sequence_8 :=  ((8&9&10&11&12&13&14&15),
                                       (8&7&10&9&12&11&14&13),
                                       (8&9&6&7&12&13&10&11),
                                       (8&7&6&5&12&11&10&9),
                                       (8&9&10&11&4&5&6&7),
                                       (8&7&10&9&4&3&6&5),
                                       (8&9&6&7&4&5&2&3),
                                       (8&7&6&5&4&3&2&1));

        SHARED VARIABLE columnFIFObuffer : columnarraytype;
        SHARED VARIABLE in_index  : INTEGER RANGE 0 TO 7 := 0;
        SHARED VARIABLE out_index : INTEGER RANGE 0 TO 7 := 0;

        -- commands
        SIGNAL command : command_type;

        -- states
        SIGNAL current_state : statebanktype := init_state & init_state &
                                   init_state & init_state & init_state &
                                   init_state &  init_state &  init_state;
        SIGNAL next_state    : statebanktype := init_state & init_state &
                                   init_state & init_state & init_state &
                                   init_state &  init_state &  init_state;

        SHARED VARIABLE current_row : rowbanktype;
        SHARED VARIABLE current_column : INTEGER range 0 to MaxColumn-1;
        SHARED VARIABLE current_bank   : INTEGER range 0 to MaxBank;

        -- MRS :
        -- Burst length
        SHARED VARIABLE BL : INTEGER RANGE 0 TO 8;-- burst_length
        -- Burst type
        SHARED VARIABLE BT : burst_addr_seq_type;
        -- CAS latency
        SHARED VARIABLE CL : INTEGER RANGE 0 TO 7;-- number of CKIn cycles
        -- Test mode
        SHARED VARIABLE TM : std_logic;
        -- Dll reset
        SHARED VARIABLE DLLreset : std_logic;
        -- write recovery (for write with auto precharge)
        SHARED VARIABLE WR : INTEGER RANGE 0 TO 7; -- number of CKIn cycles
        -- power down mode
        SHARED VARIABLE PD : power_down_mode_type;
        -- EMRS(1) :
        -- Dll enable
        SHARED VARIABLE DLLenable : std_logic;
        -- Odd-chip driver impedance control
        SHARED VARIABLE DIC : std_logic;
        -- additive latency
        SHARED VARIABLE AL : INTEGER RANGE 0 TO 4;-- number of CKIn cycles
        -- disables DQSNeg signal (0-differential , 1-single)
        SHARED VARIABLE DQSNegDis : BOOLEAN;
        -- disables output (1-outputs HiZ, 0-regular outputs)
        SHARED VARIABLE QoffHIz : std_logic;