hyb18t1g160af_120.vhd

vhdl cod for ram.For sp3e

    SIGNAL BA1_ipd             : std_ulogic := 'U';
    SIGNAL BA2_ipd             : std_ulogic := 'U';
    SIGNAL A0_ipd              : std_ulogic := 'U';
    SIGNAL A1_ipd              : std_ulogic := 'U';
    SIGNAL A2_ipd              : std_ulogic := 'U';
    SIGNAL A3_ipd              : std_ulogic := 'U';
    SIGNAL A4_ipd              : std_ulogic := 'U';
    SIGNAL A5_ipd              : std_ulogic := 'U';
    SIGNAL A6_ipd              : std_ulogic := 'U';
    SIGNAL A7_ipd              : std_ulogic := 'U';
    SIGNAL A8_ipd              : std_ulogic := 'U';
    SIGNAL A9_ipd              : std_ulogic := 'U';
    SIGNAL A10_ipd             : std_ulogic := 'U';
    SIGNAL A11_ipd             : std_ulogic := 'U';
    SIGNAL A12_ipd             : std_ulogic := 'U';
    SIGNAL DQ0_ipd             : std_ulogic := 'Z';
    SIGNAL DQ1_ipd             : std_ulogic := 'Z';
    SIGNAL DQ2_ipd             : std_ulogic := 'Z';
    SIGNAL DQ3_ipd             : std_ulogic := 'Z';
    SIGNAL DQ4_ipd             : std_ulogic := 'Z';
    SIGNAL DQ5_ipd             : std_ulogic := 'Z';
    SIGNAL DQ6_ipd             : std_ulogic := 'Z';
    SIGNAL DQ7_ipd             : std_ulogic := 'Z';
    SIGNAL DQ8_ipd             : std_ulogic := 'Z';
    SIGNAL DQ9_ipd             : std_ulogic := 'Z';
    SIGNAL DQ10_ipd            : std_ulogic := 'Z';
    SIGNAL DQ11_ipd            : std_ulogic := 'Z';
    SIGNAL DQ12_ipd            : std_ulogic := 'Z';
    SIGNAL DQ13_ipd            : std_ulogic := 'Z';
    SIGNAL DQ14_ipd            : std_ulogic := 'Z';
    SIGNAL DQ15_ipd            : std_ulogic := 'Z';
    SIGNAL UDQS_ipd            : std_ulogic := 'U';
    SIGNAL UDQSNeg_ipd         : std_ulogic := 'U';
    SIGNAL LDQS_ipd            : std_ulogic := 'U';
    SIGNAL LDQSNeg_ipd         : std_ulogic := 'U';
    SIGNAL UDM_ipd             : std_ulogic := 'U';
    SIGNAL LDM_ipd             : std_ulogic := 'U';

               -- non weak values
    SIGNAL CK_nwv              : UX01 := 'U';
    SIGNAL CKNeg_nwv           : UX01 := 'U';
    SIGNAL CKE_nwv             : UX01 := 'U';
    SIGNAL RASNeg_nwv          : UX01 := 'U';
    SIGNAL CASNeg_nwv          : UX01 := 'U';
    SIGNAL WENeg_nwv           : UX01 := 'U';
    SIGNAL CSNeg_nwv           : UX01 := 'U';
    SIGNAL BA0_nwv             : UX01 := 'U';
    SIGNAL BA1_nwv             : UX01 := 'U';
    SIGNAL BA2_nwv             : UX01 := 'U';
    SIGNAL A0_nwv              : UX01 := 'U';
    SIGNAL A1_nwv              : UX01 := 'U';
    SIGNAL A2_nwv              : UX01 := 'U';
    SIGNAL A3_nwv              : UX01 := 'U';
    SIGNAL A4_nwv              : UX01 := 'U';
    SIGNAL A5_nwv              : UX01 := 'U';
    SIGNAL A6_nwv              : UX01 := 'U';
    SIGNAL A7_nwv              : UX01 := 'U';
    SIGNAL A8_nwv              : UX01 := 'U';
    SIGNAL A9_nwv              : UX01 := 'U';
    SIGNAL A10_nwv             : UX01 := 'U';
    SIGNAL A11_nwv             : UX01 := 'U';
    SIGNAL A12_nwv             : UX01 := 'U';
    SIGNAL DQ0_nwv             : UX01 := 'U';
    SIGNAL DQ1_nwv             : UX01 := 'U';
    SIGNAL DQ2_nwv             : UX01 := 'U';
    SIGNAL DQ3_nwv             : UX01 := 'U';
    SIGNAL DQ4_nwv             : UX01 := 'U';
    SIGNAL DQ5_nwv             : UX01 := 'U';
    SIGNAL DQ6_nwv             : UX01 := 'U';
    SIGNAL DQ7_nwv             : UX01 := 'U';
    SIGNAL DQ8_nwv             : UX01 := 'U';
    SIGNAL DQ9_nwv             : UX01 := 'U';
    SIGNAL DQ10_nwv            : UX01 := 'U';
    SIGNAL DQ11_nwv            : UX01 := 'U';
    SIGNAL DQ12_nwv            : UX01 := 'U';
    SIGNAL DQ13_nwv            : UX01 := 'U';
    SIGNAL DQ14_nwv            : UX01 := 'U';
    SIGNAL DQ15_nwv            : UX01 := 'U';
    SIGNAL UDQS_nwv            : UX01 := 'U';
    SIGNAL UDQSNeg_nwv         : UX01 := 'U';
    SIGNAL LDQS_nwv            : UX01 := 'U';
    SIGNAL LDQSNeg_nwv         : UX01 := 'U';
    SIGNAL UDM_nwv             : UX01 := 'U';
    SIGNAL LDM_nwv             : UX01 := 'U';

    SIGNAL CKEInPrev           : std_ulogic := '0';
    SIGNAL CKEInnew            : std_ulogic := '0';
    SIGNAL command_changed     : bit := '0';

    SIGNAL new_rw              : std_ulogic := '0';

    SIGNAL rc_in           : std_ulogic_vector(7 downto 0) := (others => '0');
    SIGNAL rc_out          : std_ulogic_vector(7 downto 0) := (others => '0');
    SIGNAL rcd_in          : std_ulogic_vector(7 downto 0) := (others => '0');
    SIGNAL rcd_out         : std_ulogic_vector(7 downto 0) := (others => '0');
    SIGNAL ras_in          : std_ulogic_vector(7 downto 0) := (others => '0');
    SIGNAL ras_out         : std_ulogic_vector(7 downto 0) := (others => '0');
    SIGNAL rp_in           : std_ulogic_vector(7 downto 0) := (others => '0');
    SIGNAL rp_out          : std_ulogic_vector(7 downto 0) := (others => '0');
    SIGNAL rtp_in          : std_ulogic_vector(7 downto 0) := (others => '0');
    SIGNAL rtp_out         : std_ulogic_vector(7 downto 0) := (others => '0');
    SIGNAL refi_in         : std_ulogic := '0';
    SIGNAL refi_out        : std_ulogic := '0';
    SIGNAL rfc_in          : std_ulogic := '0';
    SIGNAL rfc_out         : std_ulogic := '0';
    SIGNAL rrd_in          : std_ulogic := '0';
    SIGNAL rrd_out         : std_ulogic := '0';
    SIGNAL wr_in           : std_ulogic := '0';
    SIGNAL wr_out          : std_ulogic := '0';
    SIGNAL wtr_in          : std_ulogic := '0';
    SIGNAL wtr_out         : std_ulogic := '0';
    SIGNAL xsnr_in         : std_ulogic := '0';
    SIGNAL xsnr_out        : std_ulogic := '0';

BEGIN

    ----------------------------------------------------------------------------
    -- Internal Delays
    ----------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays

    --Bank A Row to Bank A Precharge
    TRAS0  : VitalBuf (ras_out(0)  , ras_in(0)  , (tdevice_RAS, tdevice_RAS));
    TRAS1  : VitalBuf (ras_out(1)  , ras_in(1)  , (tdevice_RAS, tdevice_RAS));
    TRAS2  : VitalBuf (ras_out(2)  , ras_in(2)  , (tdevice_RAS, tdevice_RAS));
    TRAS3  : VitalBuf (ras_out(3)  , ras_in(3)  , (tdevice_RAS, tdevice_RAS));
    TRAS4  : VitalBuf (ras_out(4)  , ras_in(4)  , (tdevice_RAS, tdevice_RAS));
    TRAS5  : VitalBuf (ras_out(5)  , ras_in(5)  , (tdevice_RAS, tdevice_RAS));
    TRAS6  : VitalBuf (ras_out(6)  , ras_in(6)  , (tdevice_RAS, tdevice_RAS));
    TRAS7  : VitalBuf (ras_out(7)  , ras_in(7)  , (tdevice_RAS, tdevice_RAS));

    --Bank A Row to Bank A next Row delay
    TRC0  : VitalBuf (rc_out(0)   , rc_in(0)   , (tdevice_RC, tdevice_RC));
    TRC1  : VitalBuf (rc_out(1)   , rc_in(1)   , (tdevice_RC, tdevice_RC));
    TRC2  : VitalBuf (rc_out(2)   , rc_in(2)   , (tdevice_RC, tdevice_RC));
    TRC3  : VitalBuf (rc_out(3)   , rc_in(3)   , (tdevice_RC, tdevice_RC));
    TRC4  : VitalBuf (rc_out(4)   , rc_in(4)   , (tdevice_RC, tdevice_RC));
    TRC5  : VitalBuf (rc_out(5)   , rc_in(5)   , (tdevice_RC, tdevice_RC));
    TRC6  : VitalBuf (rc_out(6)   , rc_in(6)   , (tdevice_RC, tdevice_RC));
    TRC7  : VitalBuf (rc_out(7)   , rc_in(7)   , (tdevice_RC, tdevice_RC));

    --Bank A Row to Bank A Column delay
    TRCD0 : VitalBuf (rcd_out(0)  , rcd_in(0)  , (tdevice_RCD, tdevice_RCD));
    TRCD1 : VitalBuf (rcd_out(1)  , rcd_in(1)  , (tdevice_RCD, tdevice_RCD));
    TRCD2 : VitalBuf (rcd_out(2)  , rcd_in(2)  , (tdevice_RCD, tdevice_RCD));
    TRCD3 : VitalBuf (rcd_out(3)  , rcd_in(3)  , (tdevice_RCD, tdevice_RCD));
    TRCD4 : VitalBuf (rcd_out(4)  , rcd_in(4)  , (tdevice_RCD, tdevice_RCD));
    TRCD5 : VitalBuf (rcd_out(5)  , rcd_in(5)  , (tdevice_RCD, tdevice_RCD));
    TRCD6 : VitalBuf (rcd_out(6)  , rcd_in(6)  , (tdevice_RCD, tdevice_RCD));
    TRCD7 : VitalBuf (rcd_out(7)  , rcd_in(7)  , (tdevice_RCD, tdevice_RCD));

    --Row precharge time (Precharge to Activate the same row)
    TRP0  : VitalBuf (rp_out(0)   , rp_in(0)   , (tdevice_RP, tdevice_RP));
    TRP1  : VitalBuf (rp_out(1)   , rp_in(1)   , (tdevice_RP, tdevice_RP));
    TRP2  : VitalBuf (rp_out(2)   , rp_in(2)   , (tdevice_RP, tdevice_RP));
    TRP3  : VitalBuf (rp_out(3)   , rp_in(3)   , (tdevice_RP, tdevice_RP));
    TRP4  : VitalBuf (rp_out(4)   , rp_in(4)   , (tdevice_RP, tdevice_RP));
    TRP5  : VitalBuf (rp_out(5)   , rp_in(5)   , (tdevice_RP, tdevice_RP));
    TRP6  : VitalBuf (rp_out(6)   , rp_in(6)   , (tdevice_RP, tdevice_RP));
    TRP7  : VitalBuf (rp_out(7)   , rp_in(7)   , (tdevice_RP, tdevice_RP));

    --Internal read to precharge delay
    TRTP0 : VitalBuf (rtp_out(0)  , rtp_in(0)  , (tdevice_RTP, tdevice_RTP));
    TRTP1 : VitalBuf (rtp_out(1)  , rtp_in(1)  , (tdevice_RTP, tdevice_RTP));
    TRTP2 : VitalBuf (rtp_out(2)  , rtp_in(2)  , (tdevice_RTP, tdevice_RTP));
    TRTP3 : VitalBuf (rtp_out(3)  , rtp_in(3)  , (tdevice_RTP, tdevice_RTP));
    TRTP4 : VitalBuf (rtp_out(4)  , rtp_in(4)  , (tdevice_RTP, tdevice_RTP));
    TRTP5 : VitalBuf (rtp_out(5)  , rtp_in(5)  , (tdevice_RTP, tdevice_RTP));
    TRTP6 : VitalBuf (rtp_out(6)  , rtp_in(6)  , (tdevice_RTP, tdevice_RTP));
    TRTP7 : VitalBuf (rtp_out(7)  , rtp_in(7)  , (tdevice_RTP, tdevice_RTP));

    --Periodic refresh interval
    TREFI : VitalBuf (refi_out , refi_in , (VitalZeroDelay, tdevice_REFI));
    --Auto Refresh to another Auto Refresh or Activate command
    TRFC  : VitalBuf (rfc_out  , rfc_in  , (VitalZeroDelay, tdevice_RFC));
    --Active Bank A to Active Bank B delay
    TRRD  : VitalBuf (rrd_out  , rrd_in  , (VitalZeroDelay, tdevice_RRD));
    --Write recovery for write without Auto-Precharge
    TWR   : VitalBuf (wr_out   , wr_in   , (VitalZeroDelay, tdevice_WR));
    --Internal write to read command delay
    TWTR  : VitalBuf (wtr_out  , wtr_in  , (VitalZeroDelay, tdevice_WTR));
    --Exit Self-Refresh to non-read command
    TXSNR : VitalBuf (xsnr_out , xsnr_in , (VitalZeroDelay, tdevice_XSNR));

    --------------------------------------------------------------------------
    --  Wire Delays
    --------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
        w_01 : VitalWireDelay (CK_ipd,CK,tipd_CK);
        w_02 : VitalWireDelay (CKNeg_ipd,CKNeg,tipd_CKNeg);
        w_03 : VitalWireDelay (CKE_ipd,CKE,tipd_CKE);
        w_04 : VitalWireDelay (RASNeg_ipd,RASNeg,tipd_RASNeg);
        w_05 : VitalWireDelay (CASNeg_ipd,CASNeg,tipd_CASNeg);
        w_06 : VitalWireDelay (WENeg_ipd,WENeg,tipd_WENeg);
        w_07 : VitalWireDelay (CSNeg_ipd,CSNeg,tipd_CSNeg);
        w_08 : VitalWireDelay (BA0_ipd,BA0,tipd_BA0);
        w_09 : VitalWireDelay (BA1_ipd,BA1,tipd_BA1);
        w_10 : VitalWireDelay (BA2_ipd,BA2,tipd_BA2);
        w_11 : VitalWireDelay (A0_ipd,A0,tipd_A0);
        w_12 : VitalWireDelay (A1_ipd,A1,tipd_A1);
        w_13 : VitalWireDelay (A2_ipd,A2,tipd_A2);
        w_14 : VitalWireDelay (A3_ipd,A3,tipd_A3);
        w_15 : VitalWireDelay (A4_ipd,A4,tipd_A4);
        w_16 : VitalWireDelay (A5_ipd,A5,tipd_A5);
        w_17 : VitalWireDelay (A6_ipd,A6,tipd_A6);
        w_18 : VitalWireDelay (A7_ipd,A7,tipd_A7);
        w_19 : VitalWireDelay (A8_ipd,A8,tipd_A8);
        w_20 : VitalWireDelay (A9_ipd,A9,tipd_A9);
        w_21 : VitalWireDelay (A10_ipd,A10,tipd_A10);
        w_22 : VitalWireDelay (A11_ipd,A11,tipd_A11);
        w_23 : VitalWireDelay (A12_ipd,A12,tipd_A12);
        w_24 : VitalWireDelay (DQ0_ipd,DQ0,tipd_DQ0);
        w_25 : VitalWireDelay (DQ1_ipd,DQ1,tipd_DQ1);
        w_26 : VitalWireDelay (DQ2_ipd,DQ2,tipd_DQ2);
        w_27 : VitalWireDelay (DQ3_ipd,DQ3,tipd_DQ3);
        w_28 : VitalWireDelay (DQ4_ipd,DQ4,tipd_DQ4);
        w_29 : VitalWireDelay (DQ5_ipd,DQ5,tipd_DQ5);
        w_30 : VitalWireDelay (DQ6_ipd,DQ6,tipd_DQ6);
        w_31 : VitalWireDelay (DQ7_ipd,DQ7,tipd_DQ7);
        w_32 : VitalWireDelay (DQ8_ipd,DQ8,tipd_DQ8);
        w_33 : VitalWireDelay (DQ9_ipd,DQ9,tipd_DQ9);
        w_34 : VitalWireDelay (DQ10_ipd,DQ10,tipd_DQ10);
        w_35 : VitalWireDelay (DQ11_ipd,DQ11,tipd_DQ11);
        w_36 : VitalWireDelay (DQ12_ipd,DQ12,tipd_DQ12);
        w_37 : VitalWireDelay (DQ13_ipd,DQ13,tipd_DQ13);
        w_38 : VitalWireDelay (DQ14_ipd,DQ14,tipd_DQ14);
        w_39 : VitalWireDelay (DQ15_ipd,DQ15,tipd_DQ15);
        w_40 : VitalWireDelay (UDQS_ipd,UDQS,tipd_UDQS);
        w_41 : VitalWireDelay (UDQSNeg_ipd,UDQSNeg,tipd_UDQSNeg);
        w_42 : VitalWireDelay (LDQS_ipd,LDQS,tipd_LDQS);
        w_43 : VitalWireDelay (LDQSNeg_ipd,LDQSNeg,tipd_LDQSNeg);
        w_44 : VitalWireDelay (UDM_ipd,UDM,tipd_UDM);
        w_45 : VitalWireDelay (LDM_ipd,LDM,tipd_LDM);
    END BLOCK WireDelay;

    -- non weak values
    CK_nwv              <= To_UX01(s => CK_ipd);
    CKNeg_nwv           <= To_UX01(s => CKNeg_ipd);
    CKE_nwv             <= To_UX01(s => CKE_ipd);
    RASNeg_nwv          <= To_UX01(s => RASNeg_ipd);
    CASNeg_nwv          <= To_UX01(s => CASNeg_ipd);
    WENeg_nwv           <= To_UX01(s => WENeg_ipd);
    CSNeg_nwv           <= To_UX01(s => CSNeg_ipd);
    BA0_nwv             <= To_UX01(s => BA0_ipd);
    BA1_nwv             <= To_UX01(s => BA1_ipd);
    BA2_nwv             <= To_UX01(s => BA2_ipd);
    A0_nwv              <= To_UX01(s => A0_ipd);
    A1_nwv              <= To_UX01(s => A1_ipd);
    A2_nwv              <= To_UX01(s => A2_ipd);
    A3_nwv              <= To_UX01(s => A3_ipd);
    A4_nwv              <= To_UX01(s => A4_ipd);
    A5_nwv              <= To_UX01(s => A5_ipd);
    A6_nwv              <= To_UX01(s => A6_ipd);
    A7_nwv              <= To_UX01(s => A7_ipd);
    A8_nwv              <= To_UX01(s => A8_ipd);
    A9_nwv              <= To_UX01(s => A9_ipd);
    A10_nwv             <= To_UX01(s => A10_ipd);
    A11_nwv             <= To_UX01(s => A11_ipd);
    A12_nwv             <= To_UX01(s => A12_ipd);