hyb18t1g160af_120.vhd

vhdl cod for ram.For sp3e

------------------------------------------------------------------------------
--  File Name: hyb18t1g160af_120.vhd
------------------------------------------------------------------------------
--  Developed by HDL-Design House, www.hdl-dh.com
--  Copyright (C) 2006 Free Model Foundry;  http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:    | mod date: | changes made:
--    V1.0     S.Stojanovic  06 Feb 21   Initial release
--
------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    RAM
--  Technology: CMOS
--  Part:       hyb18t1g160af_120
--
--  Description: 1-Gbit DDR2 SDRAM
------------------------------------------------------------------------------
--  NOTES :
--
--  Simulator resolution : 1 ps
------------------------------------------------------------------------------

LIBRARY IEEE;      USE IEEE.std_logic_1164.ALL;
                   USE IEEE.VITAL_timing.ALL;
                   USE IEEE.VITAL_primitives.ALL;
                   USE STD.textio.ALL;

LIBRARY FMF;       USE FMF.gen_utils.ALL;
                   USE FMF.conversions.ALL;

------------------------------------------------------------------------------
--  ENTITY DECLARATION
------------------------------------------------------------------------------

ENTITY hyb18t1g160af_120 IS

    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_CK              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CKNeg           : VitalDelayType01 := VitalZeroDelay01;
        tipd_CKE             : VitalDelayType01 := VitalZeroDelay01;
        tipd_RASNeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_CASNeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENeg           : VitalDelayType01 := VitalZeroDelay01;
        tipd_CSNeg           : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA0             : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA1             : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA2             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12             : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ0             : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ1             : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ2             : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ3             : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ4             : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ5             : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ6             : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ7             : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ8             : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ9             : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ10            : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ11            : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ12            : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ13            : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ14            : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ15            : VitalDelayType01 := VitalZeroDelay01;
        tipd_UDQS            : VitalDelayType01 := VitalZeroDelay01;
        tipd_UDQSNeg         : VitalDelayType01 := VitalZeroDelay01;
        tipd_LDQS            : VitalDelayType01 := VitalZeroDelay01;
        tipd_LDQSNeg         : VitalDelayType01 := VitalZeroDelay01;
        tipd_UDM             : VitalDelayType01 := VitalZeroDelay01;
        tipd_LDM             : VitalDelayType01 := VitalZeroDelay01;

        -- tpd delays
        tpd_CK_DQ0              : VitalDelayType01Z := UnitDelay01Z; -- tAC, tHZ
        tpd_CK_UDQS             : VitalDelayType01Z := UnitDelay01Z;  -- tDQSCK

        -- tperiod values
        tperiod_CK               : VitalDelayType    := UnitDelay; -- tCK

        -- tsetup values: setup times
        tsetup_DQ0_UDQSNeg        : VitalDelayType    := UnitDelay; -- tDS
        tsetup_DQ0_UDQS           : VitalDelayType    := UnitDelay; -- tDS1
        tsetup_A0_CK              : VitalDelayType    := UnitDelay; -- tIS

        -- thold values: hold times
        thold_DQ0_UDQSNeg         : VitalDelayType    := UnitDelay; -- tDH
        thold_DQ0_UDQS            : VitalDelayType    := UnitDelay; -- tDH1
        thold_A0_CK               : VitalDelayType    := UnitDelay; -- tIH

        -- tdevice values: values for internal delays
        tdevice_RAS             : VitalDelayType := UnitDelay;    -- extract
        tdevice_RC              : VitalDelayType := UnitDelay;    -- extract
        tdevice_RCD             : VitalDelayType := 15 ns;
        tdevice_RP              : VitalDelayType := 15 ns;
        tdevice_REFI            : VitalDelayType := 7.8 us;
        tdevice_RFC             : VitalDelayType := 127.5 ns;
        tdevice_RRD             : VitalDelayType := 10 ns;
        tdevice_RTP             : VitalDelayType := 7.5 ns;
        tdevice_WR              : VitalDelayType := 15 ns;
        tdevice_WTR             : VitalDelayType := UnitDelay;    -- extract
        tdevice_XSNR            : VitalDelayType := 137.5 ns;

        -- tpowerup : power up time before initialization
        -- dataheet say 200 us
        tpowerup            : TIME      := 200 us;

        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        -- memory file to be loaded
        mem_file_name       : STRING    := "hyb18t1g160af_120.mem";
        UserPreload         : BOOLEAN   := TRUE;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );

    PORT (

        CK              : IN    std_ulogic := 'U'; -- clock signal
        CKNeg           : IN    std_ulogic := 'U'; -- complementary CK
        CKE             : IN    std_ulogic := 'U'; -- clock enable

        RASNeg          : IN    std_ulogic := 'U'; -- row address strobe
        CASNeg          : IN    std_ulogic := 'U'; -- column address strobe
        WENeg           : IN    std_ulogic := 'U'; -- write enable
        CSNeg           : IN    std_ulogic := 'U'; -- chip select

        BA0             : IN    std_ulogic := 'U'; --------------------
        BA1             : IN    std_ulogic := 'U'; -- bank address bus
        BA2             : IN    std_ulogic := 'U'; --------------------

        A0              : IN    std_ulogic := 'U'; --------------------
        A1              : IN    std_ulogic := 'U'; --
        A2              : IN    std_ulogic := 'U'; --
        A3              : IN    std_ulogic := 'U'; --
        A4              : IN    std_ulogic := 'U'; --
        A5              : IN    std_ulogic := 'U'; -- address signal bus
        A6              : IN    std_ulogic := 'U'; --
        A7              : IN    std_ulogic := 'U'; -- x16   : A0 - A12
        A8              : IN    std_ulogic := 'U'; --
        A9              : IN    std_ulogic := 'U'; --
        A10             : IN    std_ulogic := 'U'; -- A10/autoprecharge
        A11             : IN    std_ulogic := 'U'; --
        A12             : IN    std_ulogic := 'U';  --------------------

        DQ0             : INOUT std_ulogic := 'Z'; --------------------
        DQ1             : INOUT std_ulogic := 'Z'; --
        DQ2             : INOUT std_ulogic := 'Z'; --
        DQ3             : INOUT std_ulogic := 'Z'; --
        DQ4             : INOUT std_ulogic := 'Z'; --
        DQ5             : INOUT std_ulogic := 'Z'; --
        DQ6             : INOUT std_ulogic := 'Z'; -- data signal bus
        DQ7             : INOUT std_ulogic := 'Z'; --
        DQ8             : INOUT std_ulogic := 'Z'; --
        DQ9             : INOUT std_ulogic := 'Z'; -- x16 : D0 - D15
        DQ10            : INOUT std_ulogic := 'Z'; --
        DQ11            : INOUT std_ulogic := 'Z'; --
        DQ12            : INOUT std_ulogic := 'Z'; --
        DQ13            : INOUT std_ulogic := 'Z'; --
        DQ14            : INOUT std_ulogic := 'Z'; --
        DQ15            : INOUT std_ulogic := 'Z'; --------------------

        -- Data Strobe x16
        UDQS            : INOUT std_ulogic := 'Z'; -- data strobe (upper)
        UDQSNeg         : INOUT std_ulogic := 'Z'; -- complementary UDQS
        LDQS            : INOUT std_ulogic := 'Z'; -- data strobe (lower)
        LDQSNeg         : INOUT std_ulogic := 'Z'; -- complementary LDQS

        -- Data Mask x16
        UDM             : IN    std_ulogic := 'U'; -- data mask (upper)
        LDM             : IN    std_ulogic := 'U'  -- data mask (lower)
    );

    ATTRIBUTE VITAL_LEVEL0 of hyb18t1g160af_120 : ENTITY IS TRUE;

END hyb18t1g160af_120;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION - DYNAMIC MEMORY ALLOCATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral_dynamic_memory_allocation of hyb18t1g160af_120 IS

    ATTRIBUTE VITAL_LEVEL0
            of vhdl_behavioral_dynamic_memory_allocation : ARCHITECTURE IS TRUE;

    CONSTANT partID            : STRING  := "hyb18t1g160af_120";
    CONSTANT HiBankBit         : INTEGER := 2;
    CONSTANT HiAddrBit         : INTEGER := 12;
    CONSTANT HiRowBit          : INTEGER := 12;
    CONSTANT HiColBit          : INTEGER := 9;
    CONSTANT HiDataBit         : INTEGER := 15;

    CONSTANT MaxBank           : INTEGER := 8;
    CONSTANT MaxRow            : INTEGER := 8192;
    CONSTANT MaXColumn         : INTEGER := 1024;
    CONSTANT MaxData           : INTEGER := 65535;

    CONSTANT NoneBank          : INTEGER := 8;

--      Simulation without .sdf
    SIGNAL t_CK                : TIME := 5 ns;

    SIGNAL PoweredUp           : BOOLEAN := FALSE;

    SIGNAL tsetup_UDQS_CK      : TIME; -- tDSS (0.2*t_CK)
    SIGNAL thold_UDQS_CK       : TIME; -- tDSH (0.2*t_CK)

    SIGNAL tpwCKEnegedge       : TIME;
    SIGNAL tpwDQ0posedge       : TIME;
    SIGNAL tpwDQSposedge       : TIME;
    SIGNAL tpwA0posedge        : TIME;

    SIGNAL tpwCKposedge        : TIME; -- tCH
    SIGNAL tpwCKnegedge        : TIME; -- tCL

    SIGNAL tdevice_MRD         : TIME;   --2* tCK
    SIGNAL tdevic_RPRE         : TIME; -- (1.1*tCK)
    SIGNAL tdevic_RPST         : TIME; -- (0.6*tCK)
    SIGNAL tdevic_WPRE         : TIME; -- (0.35 * tCK)
    SIGNAL tdevic_WPST         : TIME; -- (0.35 * tCK)
    SIGNAL tdevice_XARD        : TIME;     -- 2*tCK;
    SIGNAL tdevice_XARDS       : TIME;     -- (6-AL)*tCK;
    SIGNAL tdevice_XP          : TIME;   --2*tCK;
    SIGNAL tdevice_XSRD        : TIME;   -- 200*tCK;

    -- interconnect path delay signals
    SIGNAL CK_ipd              : std_ulogic := 'U';
    SIGNAL CKNeg_ipd           : std_ulogic := 'U';
    SIGNAL CKE_ipd             : std_ulogic := 'U';
    SIGNAL RASNeg_ipd          : std_ulogic := 'U';
    SIGNAL CASNeg_ipd          : std_ulogic := 'U';
    SIGNAL WENeg_ipd           : std_ulogic := 'U';
    SIGNAL CSNeg_ipd           : std_ulogic := 'U';
    SIGNAL BA0_ipd             : std_ulogic := 'U';