📄 idt71v547.ftm

📁 vhdl cod for ram.For sp3e
💻 FTM
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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for IDT71V547 Parts</TITLE><REVISION.HISTORY>version: |  author:  | mod date: | changes made:  V1.0     R. Munden   99 AUG 12  Initial release  V1.1     R. Munden   02 MAY 20  correct port name (DQA0 to DQA0)</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>IDT71V547<FMFTIME>IDT71V547S80PF<SOURCE>Integrated Device Technology DSC-3822/1 June 1999</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:6.0:8.0) (2.0:6.0:8.0) (2.0:4.0:5.0) (2.0:6.0:8.0) (2.0:4.0:5.0) (2.0:6.0:8.0))     (IOPATH OENeg DQA0 () () (1.5:3.0:5.0) (0.0:3.0:5.0) (1.5:3.0:5.0) (0.0:3.0:5.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (10.5))    (WIDTH  (posedge CLK) (3.0))    (WIDTH  (negedge CLK) (3.0))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V547S85PF<SOURCE>Integrated Device Technology DSC-3822/1 June 1999</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:6.0:8.5) (2.0:6.0:8.5) (2.0:4.0:5.0) (2.0:6.0:8.5) (2.0:4.0:5.0) (2.0:6.0:8.5))     (IOPATH OENeg DQA0 () () (1.5:3.0:5.0) (0.0:3.0:5.0) (1.5:3.0:5.0) (0.0:3.0:5.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (11.0))    (WIDTH  (posedge CLK) (3.9))    (WIDTH  (negedge CLK) (3.9))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V547S90PF<SOURCE>Integrated Device Technology DSC-3822/1 June 1999</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:7.0:9.0) (2.0:7.0:9.0) (2.0:4.0:5.0) (2.0:7.0:9.0) (2.0:4.0:5.0) (2.0:7.0:9.0))     (IOPATH OENeg DQA0 () () (1.5:3.0:5.0) (0.0:3.0:5.0) (1.5:3.0:5.0) (0.0:3.0:5.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (12.0))    (WIDTH  (posedge CLK) (4.0))    (WIDTH  (negedge CLK) (4.0))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V547S100PF<SOURCE>Integrated Device Technology DSC-3822/1 June 1999</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:7.5:10.0) (2.0:7.5:10.0) (2.0:4.0:5.0) (2.0:7.5:10.0) (2.0:4.0:5.0) (2.0:7.5:10.0))     (IOPATH OENeg DQA0 () () (1.5:3.0:5.0) (0.0:3.0:5.0) (1.5:3.0:5.0) (0.0:3.0:5.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (15.0))    (WIDTH  (posedge CLK) (5.0))    (WIDTH  (negedge CLK) (5.0))    (SETUP A0 CLK (2.5))    (SETUP CLKENNeg CLK (2.5))    (SETUP DQA0 CLK (2.5))    (SETUP R CLK (2.5))    (SETUP ADV CLK (2.5))    (SETUP CE2 CLK (2.5))    (SETUP BWANeg CLK (2.5))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MT55L128L36FT-10<SOURCE>Micron Technology MT55L128L18F.p65 Rev. 3/99</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (3.0:6.0:7.5) (3.0:6.0:7.5) (3.0:4.0:5.0) (3.0:6.0:7.5) (3.0:4.0:5.0) (3.0:6.0:7.5))     (IOPATH OENeg DQA0 () () (1.0:3.0:5.0) (0.0:6.0:7.5) (1.0:3.0:5.0) (0.0:6.0:7.5))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (10.0))    (WIDTH  (posedge CLK) (2.5))    (WIDTH  (negedge CLK) (2.5))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MT55L128L36FT-11<SOURCE>Micron Technology MT55L128L18F.p65 Rev. 3/99</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (3.0:7.0:8.5) (3.0:7.0:8.5) (3.0:4.0:5.0) (3.0:7.0:8.5) (3.0:4.0:5.0) (3.0:7.0:8.5))     (IOPATH OENeg DQA0 () () (1.0:3.0:5.0) (0.0:6.0:7.5) (1.0:3.0:5.0) (0.0:6.0:7.5))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (11.0))    (WIDTH  (posedge CLK) (3.0))    (WIDTH  (negedge CLK) (3.0))    (SETUP A0 CLK (2.2))    (SETUP CLKENNeg CLK (2.2))    (SETUP DQA0 CLK (2.2))    (SETUP R CLK (2.2))    (SETUP ADV CLK (2.2))    (SETUP CE2 CLK (2.2))    (SETUP BWANeg CLK (2.2))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MT55L128L36FT-12<SOURCE>Micron Technology MT55L128L18F.p65 Rev. 3/99</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (3.0:7.0:9.0) (3.0:7.0:9.0) (3.0:4.0:5.0) (3.0:7.0:9.0) (3.0:4.0:5.0) (3.0:7.0:9.0))     (IOPATH OENeg DQA0 () () (1.0:3.0:5.0) (0.0:6.0:7.5) (1.0:3.0:5.0) (0.0:6.0:7.5))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (12.0))    (WIDTH  (posedge CLK) (3.0))    (WIDTH  (negedge CLK) (3.0))    (SETUP A0 CLK (2.5))    (SETUP CLKENNeg CLK (2.5))    (SETUP DQA0 CLK (2.5))    (SETUP R CLK (2.5))    (SETUP ADV CLK (2.5))    (SETUP CE2 CLK (2.5))    (SETUP BWANeg CLK (2.5))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME></BODY></FTML>
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