at25320a.vhd

vhdl cod for ram.For sp3e

            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_HOLDS_SCK,
            Violation       => Tviol_HOLDS_SCK
        );

        -- Hold Check between HOLD# and SCK \
        VitalSetupHoldCheck (
            TestSignal      => HOLDNeg_ipd,
            TestSignalName  => "HOLD#",
            RefSignal       => SCK_ipd,
            RefSignalName   => "SCK",
            HoldHigh        => thold_HOLDNeg_SCK,
            HoldLow         => thold_HOLDNeg_SCK,
            CheckEnabled    => true,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_HOLDH_SCK,
            Violation       => Tviol_HOLDH_SCK
        );

        -- Setup Check between CS# and SCK /
        VitalSetupHoldCheck (
            TestSignal      => CSNeg_ipd,
            TestSignalName  => "CS#",
            RefSignal       => SCK_ipd,
            RefSignalName   => "SCK",
            SetupLow        => tsetup_CSNeg_SCK,
            CheckEnabled    => true,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_CSS_SCK,
            Violation       => Tviol_CSS_SCK
        );

        -- Hold Check between CS# and SCK \
        VitalSetupHoldCheck (
            TestSignal      => CSNeg_ipd,
            TestSignalName  => "CS#",
            RefSignal       => SCK_ipd,
            RefSignalName   => "SCK",
            HoldLow         => thold_CSNeg_SCK,
            CheckEnabled    => true,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_CSH_SCK,
            Violation       => Tviol_CSH_SCK
        );

        -- Period Check CS#
        VitalPeriodPulseCheck (
            TestSignal      =>  CSNeg_ipd,
            TestSignalName  =>  "CS#",
            PulseWidthHigh  =>  tpw_CSNeg_posedge,
            PeriodData      =>  PD_CS,
            XOn             =>  XOn,
            MsgOn           =>  MsgOn,
            Violation       =>  Pviol_CS,
            HeaderMsg       =>  InstancePath & PartID,
            CheckEnabled    =>  true );

        -- Period Check SCK
        VitalPeriodPulseCheck (
            TestSignal      =>  SCK_ipd,
            TestSignalName  =>  "SCK",
            Period          =>  tperiod_SCK,
            PulseWidthLow   =>  tpw_SCK_negedge,
            PulseWidthHigh  =>  tpw_SCK_posedge,
            PeriodData      =>  PD_SCK,
            XOn             =>  XOn,
            MsgOn           =>  MsgOn,
            Violation       =>  Pviol_SCK,
            HeaderMsg       =>  InstancePath & PartID,
            CheckEnabled    =>  true );

        Violation := Tviol_SI_SCK            OR
                     Tviol_HOLDS_SCK          OR
                     Tviol_HOLDH_SCK          OR
                     Tviol_CSS_SCK            OR
                     Tviol_CSH_SCK            OR
                     Pviol_SCK               OR
                     Pviol_CS;

        Viol <= Violation;

        ASSERT Violation = '0'
            REPORT InstancePath & partID & ": simulation may be" &
                    " inaccurate due to timing violations"
            SEVERITY WARNING;

    END IF;
END PROCESS VITALTimingCheck;

    ----------------------------------------------------------------------------
    --  process for FSM state transition
    ----------------------------------------------------------------------------
    StateTransition : PROCESS(next_state)

    BEGIN

        current_state <= next_state;

END PROCESS StateTransition;

    ---------------------------------------------------------------------------
    --  Write cycle decode
    ---------------------------------------------------------------------------
    BusCycleDecode : PROCESS(SCK_ipd, CSNeg_ipd, HOLDNeg_ipd, SI_ipd)

        TYPE bus_cycle_type IS (STAND_BY,
                                CODE_BYTE,
                                ADDRESS_BYTES,
                                DATA_BYTES
                                );

        VARIABLE bus_cycle_state    : bus_cycle_type;

        VARIABLE data_cnt        : NATURAL := 0;
        VARIABLE addr_cnt        : NATURAL := 0;
        VARIABLE code_cnt        : NATURAL := 0;
        VARIABLE bit_cnt         : NATURAL := 0;
        VARIABLE Data_in         : std_logic_vector(255 downto 0)
                                                    := (others => '0');
        VARIABLE code            : std_logic_vector(7 downto 0);
        VARIABLE code_in         : std_logic_vector(7 downto 0);
        VARIABLE Byte_slv        : std_logic_vector(7 downto 0);
        VARIABLE addr_bytes      : std_logic_vector(HiAddrBit downto 0);
        VARIABLE Address_in      : std_logic_vector(15 downto 0);
    BEGIN

        IF rising_edge(CSNeg_ipd) AND NOT(bus_cycle_state = DATA_BYTES) THEN
            bus_cycle_state := STAND_BY;
        ELSE
        CASE bus_cycle_state IS
            WHEN STAND_BY =>
                IF falling_edge(CSNeg_ipd) THEN
                    Instruct <= NONE;
                    write <= '1';
                    code_cnt := 0;
                    addr_cnt := 0;
                    data_cnt := 0;
                    bus_cycle_state := CODE_BYTE;
                END IF;

            WHEN CODE_BYTE =>
                IF rising_edge(SCK_ipd)  AND HOLDNeg_ipd = '1' THEN
                    Code_in(code_cnt) := SI_ipd;
                    IF code_cnt = BYTE-1 THEN
                        --MSB first
                        FOR I IN 7 DOWNTO 0 LOOP
                            code(i) := code_in(7-i);
                        END LOOP;
                        CASE code IS
                            WHEN "00000110" =>
                                Instruct <= WREN;
                                bus_cycle_state := DATA_BYTES;
                            WHEN "00000100" =>
                                Instruct <= WRDI;
                                bus_cycle_state := DATA_BYTES;
                            WHEN "00000001" =>
                                Instruct <= WRSR;
                                bus_cycle_state := DATA_BYTES;
                            WHEN "00000101" =>
                                Instruct <= RDSR;
                                bus_cycle_state := DATA_BYTES;
                            WHEN "00000011" =>
                                Instruct <= READ;
                                bus_cycle_state := ADDRESS_BYTES;
                            WHEN "00000010" =>
                                Instruct <= PP;
                                bus_cycle_state := ADDRESS_BYTES;
                            WHEN others =>
                                null;
                        END CASE;
                    ELSE
                        code_cnt := code_cnt + 1;
                    END IF;
                END IF;

            WHEN ADDRESS_BYTES =>
                IF rising_edge(SCK_ipd) AND HOLDNeg_ipd = '1' THEN
                    Address_in(addr_cnt) := SI_ipd;
                    IF addr_cnt = 2*BYTE - 1 THEN
                        FOR I IN 15 DOWNTO 0 LOOP
                            addr_bytes(15-i) := Address_in(i);
                        END LOOP;
                        Address <= to_nat(addr_bytes);
                        change_addr <= '1','0' AFTER 1 ns;
                        bus_cycle_state := DATA_BYTES;
                    ELSE
                        addr_cnt := addr_cnt + 1;
                    END IF;
                END IF;

            WHEN DATA_BYTES =>
                IF falling_edge(SCK_ipd) AND CSNeg_ipd = '0' AND
                HOLDNeg_ipd = '1' THEN
                    IF Instruct = READ OR Instruct = RDSR THEN
                        read_out <= '1', '0' AFTER 1 ns;
                    END IF;
                END IF;

                IF rising_edge(SCK_ipd) AND HOLDNeg_ipd = '1' THEN
                    IF data_cnt > 255 THEN
                    --In case of PP, if more than 32 bytes are
                    --sent to the device
                        IF bit_cnt = 0 THEN
                            FOR I IN 0 TO (31*BYTE - 1) LOOP
                                Data_in(i) := Data_in(i+8);
                            END LOOP;
                        END IF;
                        Data_in(248 + bit_cnt) := SI_ipd;
                        bit_cnt := bit_cnt + 1;
                        IF bit_cnt = 8 THEN
                            bit_cnt := 0;
                        END IF;
                        data_cnt := data_cnt + 1;
                    ELSE
                        Data_in(data_cnt) := SI_ipd;
                        data_cnt := data_cnt + 1;
                        bit_cnt := 0;
                    END IF;
                END IF;

                IF rising_edge(CSNeg_ipd) THEN
                    bus_cycle_state := STAND_BY;
                    IF  HOLDNeg_ipd = '1' THEN
                        CASE Instruct IS
                            WHEN WREN | WRDI  =>
                                IF data_cnt = 0 THEN
                                    write <= '0';
                                END IF;
                            WHEN WRSR =>
                                IF data_cnt = 8 THEN
                                    write <= '0';
                                    Status_reg_in <= Data_in(7 downto 0);
                                    --MSB first
                                END IF;
                            WHEN PP =>
                                IF ((data_cnt mod 8) = 0 AND
                                    data_cnt >= BYTE) THEN
                                    write <= '0';
                                    FOR I IN 0 TO 31 LOOP
                                        FOR J IN 7 DOWNTO 0 LOOP
                                            Byte_slv(j) :=
                                            Data_in((i*8) + (7-j));
                                        END LOOP;
                                        WByte(i) <= to_nat(Byte_slv);
                                    END LOOP;
                                    IF data_cnt > 32*BYTE THEN
                                        Byte_number <= 31;
                                    ELSE
                                        Byte_number <= data_cnt/8-1;
                                    END IF;
                                END IF;
                            WHEN others =>
                                null;
                        END CASE;
                    END IF;
                END IF;

            END CASE;
        END IF;

END PROCESS BusCycleDecode;

    ---------------------------------------------------------------------------
    -- Timing control for the Write Cycle
    ---------------------------------------------------------------------------
    WriteTime : PROCESS(WSTART)
        VARIABLE wob      : time;
    BEGIN
        wob  := tdevice_WR;
        IF rising_edge(WSTART) AND WDONE = '1' THEN
            WDONE <= '0', '1' AFTER wob;
        END IF;
END PROCESS WriteTime;

    ---------------------------------------------------------------------------
    -- Main Behavior Process
    -- combinational process for next state generation
    ---------------------------------------------------------------------------
    StateGen :PROCESS(write, CSNeg, WDONE)

        VARIABLE blck   : NATURAL RANGE 0 TO BlockNum;

    BEGIN