📄 cy7c1362.ftm

📁 vhdl cod for ram.For sp3e
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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for cy7c1360c Parts</TITLE><BODY><REVISION.HISTORY>version: |  author:         | mod date: | changes made:  V1.0    M.Milanovic         05 Nov 30   Initial release  V1.1    R. Munden  	      07 Sep 07   Changed support Micron part numbers</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>cy7c1362<FMFTIME>CY7C1362A-225AJC<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-225AC<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-225BGC<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE><COMMENT>The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.25:2.05:2.80) (1.25:2.05:2.80) (1.25:2.15:3.00) (1.25:2.05:2.80) (1.25:2.15:3.00) (1.25:2.05:2.80))    (IOPATH OENeg DQA0 () () (0.00:1.40:2.80) (0.93:1.87:2.80) (0.00:1.40:2.80) (0.93:1.87:2.80))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (4.40))    (WIDTH (posedge CLK)(1.80))    (WIDTH (negedge CLK)(1.80))    (SETUP A0 CLK (1.40))    (SETUP DQA0 CLK (1.40))    (SETUP ADVNeg CLK (1.40))    (SETUP ADSCNeg CLK (1.40))    (SETUP BWANeg CLK (1.40))    (SETUP CE2 CLK (1.40))    (HOLD A0 CLK (0.40))    (HOLD DQA0 CLK (0.40))    (HOLD ADSCNeg CLK (0.40))    (HOLD BWANeg CLK (0.40))    (HOLD ADVNeg CLK (0.40))    (HOLD CE2 CLK (0.40))  )</TIMING></FMFTIME><FMFTIME>CY7C1362A-200AJC<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-200AJI<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-200AC<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-200AI<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-200BGC<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-200BGI<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE><COMMENT>The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.25:2.20:3.10) (1.25:2.20:3.10) (1.25:1.95:2.60) (1.25:2.20:3.10) (1.25:1.95:2.60) (1.25:2.20:3.10))    (IOPATH OENeg DQA0 () () (0.00:1.50:3.00) (1.00:2.00:3.00) (0.00:1.50:3.00) (1.00:2.00:3.00))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (5.00))    (WIDTH (posedge CLK)(2.00))    (WIDTH (negedge CLK)(2.00))    (SETUP A0 CLK (1.40))    (SETUP DQA0 CLK (1.40))    (SETUP ADVNeg CLK (1.40))    (SETUP ADSCNeg CLK (1.40))    (SETUP BWANeg CLK (1.40))    (SETUP CE2 CLK (1.40))    (HOLD A0 CLK (0.40))    (HOLD DQA0 CLK (0.40))    (HOLD ADSCNeg CLK (0.40))    (HOLD BWANeg CLK (0.40))    (HOLD ADVNeg CLK (0.40))    (HOLD CE2 CLK (0.40))  )</TIMING></FMFTIME><FMFTIME>CY7C1362A-166AJC_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-166AJI_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-166AC_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-166AI_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-166BGC_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-166BGI_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE><COMMENT>The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C, VCCQ=3.3V</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.25:2.40:3.50) (1.25:2.40:3.50) (1.00:1.90:2.80) (1.25:2.40:3.50) (1.00:1.90:2.80) (1.25:2.40:3.50))    (IOPATH OENeg DQA0 () () (0.00:1.75:3.50) (1.17:2.33:3.50) (0.00:1.75:3.50) (1.17:2.33:3.50))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (6.00))    (WIDTH (posedge CLK)(2.40))    (WIDTH (negedge CLK)(2.40))    (SETUP A0 CLK (1.50))    (SETUP DQA0 CLK (1.50))    (SETUP ADVNeg CLK (1.50))    (SETUP ADSCNeg CLK (1.50))    (SETUP BWANeg CLK (1.50))    (SETUP CE2 CLK (1.50))    (HOLD A0 CLK (0.50))    (HOLD DQA0 CLK (0.50))    (HOLD ADSCNeg CLK (0.50))    (HOLD BWANeg CLK (0.50))    (HOLD ADVNeg CLK (0.50))    (HOLD CE2 CLK (0.50))  )</TIMING></FMFTIME><FMFTIME>CY7C1362A-166AJC_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-166AJI_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-166AC_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-166AI_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-166BGC_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-166BGI_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE><COMMENT>The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C, VCCQ=2.5V</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.25:2.65:4.00) (1.25:2.65:4.00) (1.00:1.90:2.80) (1.25:2.65:4.00) (1.00:1.90:2.80) (1.25:2.65:4.00))    (IOPATH OENeg DQA0 () () (0.00:1.75:3.50) (1.33:2.67:4.00) (0.00:1.75:3.50) (1.33:2.67:4.00))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (6.00))    (WIDTH (posedge CLK)(2.40))    (WIDTH (negedge CLK)(2.40))    (SETUP A0 CLK (1.50))    (SETUP DQA0 CLK (1.50))    (SETUP ADVNeg CLK (1.50))    (SETUP ADSCNeg CLK (1.50))    (SETUP BWANeg CLK (1.50))    (SETUP CE2 CLK (1.50))    (HOLD A0 CLK (0.50))    (HOLD DQA0 CLK (0.50))    (HOLD ADSCNeg CLK (0.50))    (HOLD BWANeg CLK (0.50))    (HOLD ADVNeg CLK (0.50))    (HOLD CE2 CLK (0.50))  )</TIMING></FMFTIME><FMFTIME>CY7C1362A-150AJC_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-150AJI_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-150AC_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-150AI_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-150BGC_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-150BGI_3V3<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE><COMMENT>The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C, VCCQ=3.3V</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.25:2.40:3.50) (1.25:2.40:3.50) (1.25:2.65:4.00) (1.25:2.40:3.50) (1.25:2.65:4.00) (1.25:2.40:3.50))    (IOPATH OENeg DQA0 () () (0.00:1.75:3.50) (1.17:2.33:3.50) (0.00:1.75:3.50) (1.17:2.33:3.50))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (6.70))    (WIDTH (posedge CLK)(2.60))    (WIDTH (negedge CLK)(2.60))    (SETUP A0 CLK (2.00))    (SETUP DQA0 CLK (2.00))    (SETUP ADVNeg CLK (2.00))    (SETUP ADSCNeg CLK (2.00))    (SETUP BWANeg CLK (2.00))    (SETUP CE2 CLK (2.00))    (HOLD A0 CLK (0.50))    (HOLD DQA0 CLK (0.50))    (HOLD ADSCNeg CLK (0.50))    (HOLD BWANeg CLK (0.50))    (HOLD ADVNeg CLK (0.50))    (HOLD CE2 CLK (0.50))  )</TIMING></FMFTIME><FMFTIME>CY7C1362A-150AJC_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-150AJI_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-150AC_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-150AI_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-150BGC_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE>CY7C1362A-150BGI_2V5<SOURCE>Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003</SOURCE><COMMENT>The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C, VCCQ=2.5V</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.50:3.00:4.50) (1.50:3.00:4.50) (1.25:2.65:4.00) (1.50:3.00:4.50) (1.25:2.65:4.00) (1.50:3.00:4.50))    (IOPATH OENeg DQA0 () () (0.00:1.75:3.50) (1.50:3.00:4.50) (0.00:1.75:3.50) (1.50:3.00:4.50))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (6.70))    (WIDTH (posedge CLK)(2.60))    (WIDTH (negedge CLK)(2.60))    (SETUP A0 CLK (2.00))    (SETUP DQA0 CLK (2.00))    (SETUP ADVNeg CLK (2.00))    (SETUP ADSCNeg CLK (2.00))    (SETUP BWANeg CLK (2.00))    (SETUP CE2 CLK (2.00))    (HOLD A0 CLK (0.50))    (HOLD DQA0 CLK (0.50))    (HOLD ADSCNeg CLK (0.50))    (HOLD BWANeg CLK (0.50))    (HOLD ADVNeg CLK (0.50))    (HOLD CE2 CLK (0.50))  )</TIMING></FMFTIME><FMFTIME>MT58L512L18PT-6<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PT-6IT<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PS-6<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PS-6IT<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PF-6<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PF-6IT<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE><COMMENT>The values listed are for VDD=+3.3V+0.3V/-0.165V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.50:2.50:3.50) (1.50:2.50:3.50) (1.17:2.33:3.50) (1.50:2.50:3.50) (1.17:2.33:3.50) (1.50:2.50:3.50))    (IOPATH OENeg DQA0 () () (1.17:2.33:3.50) (1.17:2.33:3.50) (1.17:2.33:3.50) (1.17:2.33:3.50))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (6.00))    (WIDTH (posedge CLK)(2.30))    (WIDTH (negedge CLK)(2.30))    (SETUP A0 CLK (1.50))    (SETUP DQA0 CLK (1.50))    (SETUP ADVNeg CLK (1.50))    (SETUP ADSCNeg CLK (1.50))    (SETUP BWANeg CLK (1.50))    (SETUP CE2 CLK (1.50))    (HOLD A0 CLK (0.50))    (HOLD DQA0 CLK (0.50))    (HOLD ADSCNeg CLK (0.50))    (HOLD BWANeg CLK (0.50))    (HOLD ADVNeg CLK (0.50))    (HOLD CE2 CLK (0.50))  )</TIMING></FMFTIME><FMFTIME>MT58L512L18PT-7.5<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PT-7.5IT<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PS-7.5<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PS-7.5IT<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PF-7.5<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PF-7.5IT<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE><COMMENT>The values listed are for VDD=+3.3V+0.3V/-0.165V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.50:2.75:4.00) (1.50:2.75:4.00) (1.40:2.80:4.20) (1.50:2.75:4.00) (1.40:2.80:4.20) (1.50:2.75:4.00))    (IOPATH OENeg DQA0 () () (1.40:2.80:4.20) (1.40:2.80:4.20) (1.40:2.80:4.20) (1.40:2.80:4.20))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (7.50))    (WIDTH (posedge CLK)(2.50))    (WIDTH (negedge CLK)(2.50))    (SETUP A0 CLK (1.50))    (SETUP DQA0 CLK (1.50))    (SETUP ADVNeg CLK (1.50))    (SETUP ADSCNeg CLK (1.50))    (SETUP BWANeg CLK (1.50))    (SETUP CE2 CLK (1.50))    (HOLD A0 CLK (0.50))    (HOLD DQA0 CLK (0.50))    (HOLD ADSCNeg CLK (0.50))    (HOLD BWANeg CLK (0.50))    (HOLD ADVNeg CLK (0.50))    (HOLD CE2 CLK (0.50))  )</TIMING></FMFTIME><FMFTIME>MT58L512L18PT-10<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PT-10IT<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PS-10<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PS-10IT<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PF-10<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE>MT58L512L18PF-10IT<SOURCE>Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02</SOURCE><COMMENT>The values listed are for VDD=+3.3V+0.3V/-0.165V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.67:3.33:5.00) (1.67:3.33:5.00) (1.67:3.33:5.00) (1.67:3.33:5.00) (1.67:3.33:5.00) (1.67:3.33:5.00))    (IOPATH OENeg DQA0 () () (1.50:3.00:4.50) (1.67:3.33:5.00) (1.50:3.00:4.50) (1.67:3.33:5.00))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (10.00))    (WIDTH (posedge CLK)(3.00))    (WIDTH (negedge CLK)(3.00))    (SETUP A0 CLK (2.00))    (SETUP DQA0 CLK (2.00))    (SETUP ADVNeg CLK (2.00))    (SETUP ADSCNeg CLK (2.00))    (SETUP BWANeg CLK (2.00))    (SETUP CE2 CLK (2.00))    (HOLD A0 CLK (0.50))    (HOLD DQA0 CLK (0.50))    (HOLD ADSCNeg CLK (0.50))    (HOLD BWANeg CLK (0.50))    (HOLD ADVNeg CLK (0.50))    (HOLD CE2 CLK (0.50))  )</TIMING></FMFTIME><FMFTIME>GS88118AT-250<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE>GS88118AT-250I<SOURCE>Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002</SOURCE><COMMENT>The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.50:2.00:2.50) (1.50:2.00:2.50) (1.50:2.00:2.30) (1.50:2.00:2.50) (1.50:2.00:2.30) (1.50:2.00:2.50))    (IOPATH OENeg DQA0 () () (0.77:1.53:2.30) (0.77:1.53:2.30) (0.77:1.53:2.30) (0.77:1.53:2.30))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (4.00))    (WIDTH (posedge CLK)(1.30))    (WIDTH (negedge CLK)(1.50))    (SETUP A0 CLK (1.20))    (SETUP DQA0 CLK (1.20))    (SETUP ADVNeg CLK (1.20))    (SETUP ADSCNeg CLK (1.20))    (SETUP BWANeg CLK (1.20))    (SETUP CE2 CLK (1.20))    (HOLD A0 CLK (0.20))    (HOLD DQA0 CLK (0.20))    (HOLD ADSCNeg CLK (0.20))    (HOLD BWANeg CLK (0.20))    (HOLD ADVNeg CLK (0.20))    (HOLD CE2 CLK (0.20))  )
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