mt54w1mh18.vhd

vhdl cod for ram.For sp3e

        w_29 : VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_30 : VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_31 : VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_32 : VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_33 : VitalWireDelay (D8_ipd, D8, tipd_D8);
        w_34 : VitalWireDelay (D9_ipd, D9, tipd_D9);
        w_35 : VitalWireDelay (D10_ipd, D10, tipd_D10);
        w_36 : VitalWireDelay (D11_ipd, D11, tipd_D11);
        w_37 : VitalWireDelay (D12_ipd, D12, tipd_D12);
        w_38 : VitalWireDelay (D13_ipd, D13, tipd_D13);
        w_39 : VitalWireDelay (D14_ipd, D14, tipd_D14);
        w_40 : VitalWireDelay (D15_ipd, D15, tipd_D15);
        w_41 : VitalWireDelay (D16_ipd, D16, tipd_D16);
        w_42 : VitalWireDelay (D17_ipd, D17, tipd_D17);
        w_53 : VitalWireDelay (RNeg_ipd, RNeg, tipd_RNeg);
        w_54 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
        w_55 : VitalWireDelay (BW0Neg_ipd, BW0Neg, tipd_BW0Neg);
        w_56 : VitalWireDelay (BW1Neg_ipd, BW1Neg, tipd_BW1Neg);
        w_57 : VitalWireDelay (K_ipd, K, tipd_K);
        w_58 : VitalWireDelay (KNeg_ipd, KNeg, tipd_KNeg);
        w_59 : VitalWireDelay (C_ipd, C, tipd_C);
        w_60 : VitalWireDelay (CNeg_ipd, CNeg, tipd_CNeg);
        w_61 : VitalWireDelay (TMS_ipd, TMS, tipd_TMS);
        w_62 : VitalWireDelay (TDI_ipd, TDI, tipd_TDI);
        w_63 : VitalWireDelay (TCK_ipd, TCK, tipd_TCK);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK
        PORT (
            DLLNegIn        : IN    std_logic  := 'U';  
            BW0NIn          : IN    std_ulogic := 'U';
            BW1NIn          : IN    std_ulogic := 'U';
            Dat0In          : IN    std_logic_vector(HiDbit downto 0);
            Dat1In          : IN    std_logic_vector(HiDbit downto 0);
            DataOut         : OUT   std_logic_vector(17 downto 0)
                                                     := (others => 'Z');
            CIn             : IN    std_ulogic := 'U';
            CNegIn          : IN    std_ulogic := 'U';
            KIn             : IN    std_ulogic := 'U';
            KNegIn          : IN    std_ulogic := 'U';
            AddressIn       : IN    std_logic_vector(HiAbit downto 0);
            RIn             : IN    std_ulogic := 'U';
            WIn             : IN    std_ulogic := 'U';
            CQOut           : OUT   std_ulogic := 'U';
            CQNegOut        : OUT   std_ulogic := 'U'
        );
        PORT MAP (
            Dat0In(0) => D0_ipd,
            Dat0In(1) => D1_ipd,
            Dat0In(2) => D2_ipd,
            Dat0In(3) => D3_ipd,
            Dat0In(4) => D4_ipd,
            Dat0In(5) => D5_ipd,
            Dat0In(6) => D6_ipd,
            Dat0In(7) => D7_ipd,
            Dat0In(8) => D8_ipd,
            Dat1In(0) => D9_ipd,
            Dat1In(1) => D10_ipd,
            Dat1In(2) => D11_ipd,
            Dat1In(3) => D12_ipd,
            Dat1In(4) => D13_ipd,
            Dat1In(5) => D14_ipd,
            Dat1In(6) => D15_ipd,
            Dat1In(7) => D16_ipd,
            Dat1In(8) => D17_ipd,
            DataOut(0) =>  Q0,
            DataOut(1) =>  Q1,
            DataOut(2) =>  Q2,
            DataOut(3) =>  Q3,
            DataOut(4) =>  Q4,
            DataOut(5) =>  Q5,
            DataOut(6) =>  Q6,
            DataOut(7) =>  Q7,
            DataOut(8) =>  Q8,
            DataOut(9) =>  Q9,
            DataOut(10) =>  Q10,
            DataOut(11) =>  Q11,
            DataOut(12) =>  Q12,
            DataOut(13) =>  Q13,
            DataOut(14) =>  Q14,
            DataOut(15) =>  Q15,
            DataOut(16) =>  Q16,
            DataOut(17) =>  Q17,
            AddressIn(0) => A0_ipd,
            AddressIn(1) => A1_ipd,
            AddressIn(2) => A2_ipd,
            AddressIn(3) => A3_ipd,
            AddressIn(4) => A4_ipd,
            AddressIn(5) => A5_ipd,
            AddressIn(6) => A6_ipd,
            AddressIn(7) => A7_ipd,
            AddressIn(8) => A8_ipd,
            AddressIn(9) => A9_ipd,
            AddressIn(10) => A10_ipd,
            AddressIn(11) => A11_ipd,
            AddressIn(12) => A12_ipd,
            AddressIn(13) => A13_ipd,
            AddressIn(14) => A14_ipd,
            AddressIn(15) => A15_ipd,
            AddressIn(16) => A16_ipd,
            AddressIn(17) => A17_ipd,
            AddressIn(18) => A18_ipd,
            BW0NIn => BW0Neg_ipd,
            BW1NIn => BW1Neg_ipd,
            CIn => C_ipd,
            CNegIn => CNeg_ipd,
            KIn => K_ipd,
            KNegIn => KNeg_ipd,
            RIn => RNeg_ipd,
            WIn => WNeg_ipd,
            CQOut => CQ,
            CQNegOut => CQNeg,
            DLLNegIn => DLLNeg_ipd            
        );

        SIGNAL Q_zd     : std_logic_vector(17 DOWNTO 0);
        SIGNAL KTRIG    : std_ulogic;
        SIGNAL CTRIG    : std_ulogic;
        SIGNAL KCTRIG   : std_ulogic;
        SIGNAL KCTRIGN  : std_ulogic;

        SIGNAL CPERIOD  : time := 6 ns;       -- C period     
        SIGNAL KPERIOD  : time := 6 ns;       -- K period         
        SIGNAL CInt     : std_ulogic := '0';
        SIGNAL CNegInt  : std_ulogic := '0';  
     
        SIGNAL Ctemp    : std_ulogic := '0';
        SIGNAL Ktemp    : std_ulogic := '0';        

        SIGNAL CHalfPer : time := 5 ns;
        SIGNAL Cdlldelay: time := 0 ns;       
        SIGNAL KHalfPer : time := 5 ns;
        SIGNAL Kdlldelay: time := 0 ns;   
                
        TYPE cmode IS (c, k);
        SIGNAL mode     : cmode := c;         
       
    BEGIN

        ----------------------------------------------
        -- DLL model functional section            ---    
        ----------------------------------------------
        C_DLL: PROCESS(CIn, Ctemp)

        VARIABLE CIn_period    : Time := 1 ms;
        VARIABLE prev_CIn      : Time := 0 ns;
        VARIABLE Ctemp_period  : Time := 0 ns;
        VARIABLE Ctemp_period1 : Time := 0 ns;
        VARIABLE Ctemp_period2 : Time := 0 ns;
        VARIABLE prev_Ctemp    : Time := 0 ns;
        VARIABLE dll_lock      : BOOLEAN := false;
        VARIABLE toggle1       : boolean;
        VARIABLE toggle2       : boolean;

        BEGIN               
        IF mode = c THEN
            IF rising_edge(CIn) THEN
                CIn_period := NOW - prev_CIn;
                prev_CIn := NOW;
                IF CIn_period > 30 ns THEN
                    dll_lock := false;
                    ASSERT false
                        REPORT "C mode DLL reseting"
                        SEVERITY note;
                END IF;
            END IF;

            IF rising_edge(Ctemp) THEN
                Ctemp_period := NOW - prev_Ctemp;
                prev_Ctemp := NOW;
                IF toggle1 AND toggle2 AND not(dll_lock) THEN
                    IF Ctemp_period > CIn_period THEN
                        Chalfper <= Chalfper - 51 ps;
                        dll_lock := false;
                    ELSIF Ctemp_period < CIn_period THEN
                        Chalfper <= Chalfper + 7 ps;
                        dll_lock := false;
                    ELSIF Ctemp_period = Ctemp_period2 THEN -- stable?
                        dll_lock := true;
                        ASSERT false
                            REPORT "C mode DLL lock achieved"
                            SEVERITY note;
                    ELSE
                        Ctemp_period2 := Ctemp_period1;
                        Ctemp_period1 := Ctemp_period;
                    END IF;
                END IF;
                toggle1 := not toggle1;
                IF toggle1 THEN
                    toggle2 := not toggle2;
                ELSE
                    Cdlldelay <= 0 ps;
                END IF;
            END IF;

            IF rising_edge(Ctemp) AND dll_lock AND toggle1 AND toggle2 THEN
                IF (prev_CIn + tpd_C_Q1) < NOW THEN
                    IF Cdlldelay < CIn_period THEN
                        Cdlldelay <= Cdlldelay - 60 ps;
                    END IF;
                END IF;
            END IF;
        END IF;
                            
        END PROCESS C_DLL;

        C_temp : PROCESS(Ctemp) -- generating internal clock from DLL
        BEGIN
            Ctemp <= not(Ctemp) AFTER CHalfPer + Cdlldelay;
        END PROCESS C_temp;

        K_DLL: PROCESS(KIn, Ktemp)

        VARIABLE KIn_period   : Time := 1 ms;
        VARIABLE prev_KIn     : Time := 0 ns;
        VARIABLE Ktemp_period : Time := 0 ns;
        VARIABLE Ktemp_period1 : Time := 0 ns;
        VARIABLE Ktemp_period2 : Time := 0 ns;
        VARIABLE prev_Ktemp   : Time := 0 ns;
        VARIABLE dll_lock     : BOOLEAN := false;
        VARIABLE toggle1      : boolean;
        VARIABLE toggle2      : boolean;

        BEGIN
        IF mode = k THEN
            IF rising_edge(KIn) THEN
                KIn_period := NOW - prev_KIn;
                prev_KIn := NOW;
                IF KIn_period > 30 ns THEN
                    dll_lock := false;
                    ASSERT false
                        REPORT "K mode DLL reseting"
                        SEVERITY note;
                END IF;
            END IF;

            IF rising_edge(Ktemp) THEN
                Ktemp_period := NOW - prev_Ktemp;
                prev_Ktemp := NOW;
                IF toggle1 AND toggle2 AND not(dll_lock) THEN
                    IF Ktemp_period > KIn_period THEN
                        Khalfper <= Khalfper - 51 ps;
                        dll_lock := false;
                    ELSIF Ktemp_period < KIn_period THEN
                        Khalfper <= Khalfper + 7 ps;
                        dll_lock := false;
                    ELSIF Ktemp_period = Ktemp_period2 THEN -- stable?
                        dll_lock := true;
                        ASSERT false
                            REPORT "K mode DLL lock achieved"
                            SEVERITY note;
                    ELSE
                        Ktemp_period2 := Ktemp_period1;
                        Ktemp_period1 := Ktemp_period;
                    END IF;
                END IF;
                toggle1 := not toggle1;
                IF toggle1 THEN
                    toggle2 := not toggle2;
                ELSE
                    Kdlldelay <= 0 ps;
                END IF;
            END IF;

            IF rising_edge(Ktemp) AND dll_lock AND toggle1 AND toggle2 THEN
                IF (prev_KIn + tpd_C_Q1) < NOW THEN
                    IF Kdlldelay < KIn_period THEN
                        Kdlldelay <= Kdlldelay - 60 ps;
                    END IF;
                END IF;
            END IF;
        END IF;

        END PROCESS K_DLL;

        K_temp : PROCESS(Ktemp) -- generating internal clock from DLL
        BEGIN
            Ktemp <= not(Ktemp)  AFTER KHalfPer + Kdlldelay;
        END PROCESS K_temp;

        C_int : PROCESS (CIn, Ctemp, KIn, Ktemp)-- Passing clock based on DLL_EN
        BEGIN           
            IF (not DLLNegIn='0') THEN        
                IF mode = c THEN
                    CInt <= TRANSPORT Ctemp;
                    CNegInt <= TRANSPORT not Ctemp;
                ELSIF mode = k THEN
                    CInt <= TRANSPORT Ktemp;
                    CNegInt <= TRANSPORT not Ktemp;
                END IF;
            ELSE 
                IF mode = c THEN
                    CInt <= CIn ;
                    CNegInt <= CNegIn ;
                ELSE   
                    CInt <= KIn;
                    CNegInt <= KNegIn;                
                END IF;
            END IF;    
        END PROCESS C_int;
        
        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Behavior : PROCESS (BW0NIn, BW1NIn, CInt, CNegInt, KIn,
                            KNegIn, RIn, WIn, AddressIn, Dat0In, Dat1In,
                            KTRIG, CTRIG, KCTRIG, KCTRIGN)

            -- Timing Check Variables
            VARIABLE Tviol_A0_K         : X01 := '0';
            VARIABLE TD_A0_K            : VitalTimingDataType;