mt55l128l36p.vhd

vhdl cod for ram.For sp3e

        VARIABLE TD_R_CLK      : VitalTimingDataType;

        VARIABLE Tviol_ADV_CLK : X01 := '0';
        VARIABLE TD_ADV_CLK    : VitalTimingDataType;

        VARIABLE Tviol_CE1_CLK : X01 := '0';
        VARIABLE TD_CE1_CLK    : VitalTimingDataType;

        VARIABLE Tviol_CE2_CLK : X01 := '0';
        VARIABLE TD_CE2_CLK    : VitalTimingDataType;

        VARIABLE Tviol_CE2Neg_CLK : X01 := '0';
        VARIABLE TD_CE2Neg_CLK    : VitalTimingDataType;

        VARIABLE Tviol_BW1_CLK : X01 := '0';
        VARIABLE TD_BW1_CLK    : VitalTimingDataType;

        VARIABLE Tviol_BW2_CLK : X01 := '0';
        VARIABLE TD_BW2_CLK    : VitalTimingDataType;

        VARIABLE Tviol_BW3_CLK : X01 := '0';
        VARIABLE TD_BW3_CLK    : VitalTimingDataType;

        VARIABLE Tviol_BW4_CLK : X01 := '0';
        VARIABLE TD_BW4_CLK    : VitalTimingDataType;

        VARIABLE PD_CLK        : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE Pviol_CLK     : X01 := '0';

        -- Functionality Results Variables
        VARIABLE IO_zd       : std_logic_vector(35 downto 0) := (others => 'X');
        VARIABLE Violation  : X01 := '0';

        -- Output Glitch Detection Variables
        VARIABLE IO_GlitchData : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            VitalSetupHoldCheck (
                TestSignal      =>  CLKENNeg_ipd,
                TestSignalName  => "CLKENNeg_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_CLKENNeg_CLK,
                SetupLow        =>  tsetup_CLKENNeg_CLK,
                HoldHigh        =>  thold_CLKENNeg_CLK,
                HoldLow         =>  thold_CLKENNeg_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_CLKEN_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_CLKEN_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A0_ipd,
                TestSignalName  => "A0_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A0_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A0_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A1_ipd,
                TestSignalName  => "A1_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A1_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A1_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A2_ipd,
                TestSignalName  => "A2_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A2_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A2_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A3_ipd,
                TestSignalName  => "A3_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A3_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A3_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A4_ipd,
                TestSignalName  => "A4_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A4_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A4_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A5_ipd,
                TestSignalName  => "A5_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A5_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A5_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A6_ipd,
                TestSignalName  => "A6_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A6_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A6_CLK);
            VitalSetupHoldCheck (
                TestSignal      =>  A7_ipd,
                TestSignalName  => "A7_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A7_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A7_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A8_ipd,
                TestSignalName  => "A8_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A8_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A8_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A9_ipd,
                TestSignalName  => "A9_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A9_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A9_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A10_ipd,
                TestSignalName  => "A10_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A10_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A10_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A11_ipd,
                TestSignalName  => "A11_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A11_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A11_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A12_ipd,
                TestSignalName  => "A12_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,
                HoldHigh        =>  thold_A0_CLK,
                HoldLow         =>  thold_A0_CLK,
                CheckEnabled    =>  TRUE,
                RefTransition   =>  '/',
                HeaderMsg       =>  InstancePath & "/mt55l128l36p",
                TimingData      =>  TD_A12_CLK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Tviol_A12_CLK);

            VitalSetupHoldCheck (
                TestSignal      =>  A13_ipd,
                TestSignalName  => "A13_ipd",
                RefSignal       =>  CLK_ipd,
                RefSignalName   =>  "CLK_ipd",
                SetupHigh       =>  tsetup_A0_CLK,
                SetupLow        =>  tsetup_A0_CLK,