mt55l128l36p.vhd

vhdl cod for ram.For sp3e

    SIGNAL BONeg_nwv           : std_ulogic := 'X';

    SIGNAL addr_in, addr_out : STD_LOGIC_VECTOR (16 DOWNTO 0) 
                               := (OTHERS => '0');
    SIGNAL ce, doe             : std_ulogic := 'X';
    SIGNAL bwa_in, bwb_in, bwc_in, bwd_in, ce_in, rw_in 
                               : STD_LOGIC_VECTOR(1 DOWNTO 0) := "XX";
    SIGNAL bcount : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'X');
    SIGNAL addr_nat : NATURAL := 0;

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_2 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_3 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_4 : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_5 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_6 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_7 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_8 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_9 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_10 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_11 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_12 : VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_13 : VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_14 : VitalWireDelay (A13_ipd, A13, tipd_A13);
        w_15 : VitalWireDelay (A14_ipd, A14, tipd_A14);
        w_16 : VitalWireDelay (A15_ipd, A15, tipd_A15);
        w_17 : VitalWireDelay (A16_ipd, A16, tipd_A16);
        w_20 : VitalWireDelay (IO0_ipd, IO0, tipd_IO0);
        w_21 : VitalWireDelay (IO1_ipd, IO1, tipd_IO1);
        w_22 : VitalWireDelay (IO2_ipd, IO2, tipd_IO2);
        w_23 : VitalWireDelay (IO3_ipd, IO3, tipd_IO3);
        w_24 : VitalWireDelay (IO4_ipd, IO4, tipd_IO4);
        w_25 : VitalWireDelay (IO5_ipd, IO5, tipd_IO5);
        w_26 : VitalWireDelay (IO6_ipd, IO6, tipd_IO6);
        w_27 : VitalWireDelay (IO7_ipd, IO7, tipd_IO7);
        w_28 : VitalWireDelay (IO8_ipd, IO8, tipd_IO8);
        w_29 : VitalWireDelay (IO9_ipd, IO9, tipd_IO9);
        w_30 : VitalWireDelay (IO10_ipd, IO10, tipd_IO10);
        w_31 : VitalWireDelay (IO11_ipd, IO11, tipd_IO11);
        w_32 : VitalWireDelay (IO12_ipd, IO12, tipd_IO12);
        w_33 : VitalWireDelay (IO13_ipd, IO13, tipd_IO13);
        w_34 : VitalWireDelay (IO14_ipd, IO14, tipd_IO14);
        w_35 : VitalWireDelay (IO15_ipd, IO15, tipd_IO15);
        w_36 : VitalWireDelay (IO16_ipd, IO16, tipd_IO16);
        w_37 : VitalWireDelay (IO17_ipd, IO17, tipd_IO17);
        w_38 : VitalWireDelay (IO18_ipd, IO18, tipd_IO18);
        w_39 : VitalWireDelay (IO19_ipd, IO19, tipd_IO19);
        w_40 : VitalWireDelay (IO20_ipd, IO20, tipd_IO20);
        w_41 : VitalWireDelay (IO21_ipd, IO21, tipd_IO21);
        w_42 : VitalWireDelay (IO22_ipd, IO22, tipd_IO22);
        w_43 : VitalWireDelay (IO23_ipd, IO23, tipd_IO23);
        w_44 : VitalWireDelay (IO24_ipd, IO24, tipd_IO24);
        w_45 : VitalWireDelay (IO25_ipd, IO25, tipd_IO25);
        w_46 : VitalWireDelay (IO26_ipd, IO26, tipd_IO26);
        w_47 : VitalWireDelay (IO27_ipd, IO27, tipd_IO27);
        w_48 : VitalWireDelay (IO28_ipd, IO28, tipd_IO28);
        w_49 : VitalWireDelay (IO29_ipd, IO29, tipd_IO29);
        w_50 : VitalWireDelay (IO30_ipd, IO30, tipd_IO30);
        w_51 : VitalWireDelay (IO31_ipd, IO31, tipd_IO31);
        w_52 : VitalWireDelay (IO32_ipd, IO32, tipd_IO32);
        w_53 : VitalWireDelay (IO33_ipd, IO33, tipd_IO33);
        w_54 : VitalWireDelay (IO34_ipd, IO34, tipd_IO34);
        w_55 : VitalWireDelay (IO35_ipd, IO35, tipd_IO35);
        w_56 : VitalWireDelay (ADV_ipd, ADV, tipd_ADV);
        w_57 : VitalWireDelay (R_ipd, R, tipd_R);
        w_58 : VitalWireDelay (CLKENNeg_ipd, CLKENNeg, tipd_CLKENNeg);
        w_59 : VitalWireDelay (BW4Neg_ipd, BW4Neg, tipd_BW4Neg);
        w_60 : VitalWireDelay (BW3Neg_ipd, BW3Neg, tipd_BW3Neg);
        w_70 : VitalWireDelay (BW2Neg_ipd, BW2Neg, tipd_BW2Neg);
        w_71 : VitalWireDelay (BW1Neg_ipd, BW1Neg, tipd_BW1Neg);
        w_72 : VitalWireDelay (CE1Neg_ipd, CE1Neg, tipd_CE1Neg);
        w_73 : VitalWireDelay (CE2Neg_ipd, CE2Neg, tipd_CE2Neg);
        w_74 : VitalWireDelay (CE2_ipd, CE2, tipd_CE2);
        w_75 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_76 : VitalWireDelay (BONeg_ipd, BONeg, tipd_BONeg);
        w_77 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);
        w_78 : VitalWireDelay (ZZ_ipd, ZZ, tipd_ZZ);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent procedure calls
    ----------------------------------------------------------------------------
    ce <= NOT(CE1Neg_ipd) AND NOT(CE2Neg_ipd) AND CE2_ipd;
    doe <= ce_in(0) AND NOT(rw_in(0)) AND NOT(OENeg_ipd);

    addr_nat <= To_nat(addr_out);
    ADV_nwv <= To_X01(ADV_ipd);
    BONeg_nwv <= To_X01(BONeg_ipd);
    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
    VitalBehavior : PROCESS (CLK_ipd, R_ipd, ADV_ipd, CLKENNeg_ipd, CE1Neg_ipd,
               CE2Neg_ipd, CE2_ipd, BW1Neg_ipd, BW2Neg_ipd, BW3Neg_ipd, 
               BW4Neg_ipd, A16_ipd, A15_ipd, A14_ipd, A13_ipd, A12_ipd,
               A11_ipd, A10_ipd, A9_ipd, A8_ipd, A7_ipd, A6_ipd, A5_ipd,
               A4_ipd, A3_ipd, A2_ipd, A1_ipd, A0_ipd, OENeg_ipd,
               IO35_ipd, IO34_ipd, IO33_ipd, IO32_ipd, IO31_ipd, IO30_ipd,
               IO29_ipd, IO28_ipd, IO27_ipd, IO26_ipd, IO25_ipd, IO24_ipd,
               IO23_ipd, IO22_ipd, IO21_ipd, IO20_ipd, IO19_ipd, IO18_ipd,
               IO17_ipd, IO16_ipd, IO15_ipd, IO14_ipd, IO13_ipd, IO12_ipd,
               IO11_ipd, IO10_ipd, IO9_ipd, IO8_ipd, IO7_ipd, IO6_ipd, IO5_ipd,
               IO4_ipd, IO3_ipd, IO2_ipd, IO1_ipd, IO0_ipd)

    TYPE mem_array IS ARRAY ((2 ** 19) - 1 DOWNTO 0) OF 
                                      STD_LOGIC_VECTOR(8 DOWNTO 0);
    VARIABLE ram0 : mem_array;
    VARIABLE ram1 : mem_array;
    VARIABLE ram2 : mem_array;
    VARIABLE ram3 : mem_array;
    CONSTANT HiZ  : STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => 'Z');
    VARIABLE btemp : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'X');
    VARIABLE addr : STD_LOGIC_VECTOR (16 DOWNTO 0) := (OTHERS => 'X');
    VARIABLE Dq   : STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => 'X');

        -- Timing Check Variables
        VARIABLE Tviol_IO0_CLK  : X01 := '0';
        VARIABLE TD_IO0_CLK     : VitalTimingDataType;

        VARIABLE Tviol_IO1_CLK  : X01 := '0';
        VARIABLE TD_IO1_CLK     : VitalTimingDataType;

        VARIABLE Tviol_IO2_CLK  : X01 := '0';
        VARIABLE TD_IO2_CLK     : VitalTimingDataType;

        VARIABLE Tviol_IO3_CLK  : X01 := '0';
        VARIABLE TD_IO3_CLK     : VitalTimingDataType;

        VARIABLE Tviol_IO4_CLK  : X01 := '0';
        VARIABLE TD_IO4_CLK     : VitalTimingDataType;

        VARIABLE Tviol_IO5_CLK  : X01 := '0';
        VARIABLE TD_IO5_CLK     : VitalTimingDataType;

        VARIABLE Tviol_IO6_CLK  : X01 := '0';
        VARIABLE TD_IO6_CLK     : VitalTimingDataType;

        VARIABLE Tviol_IO7_CLK  : X01 := '0';
        VARIABLE TD_IO7_CLK     : VitalTimingDataType;

        VARIABLE Tviol_IO8_CLK  : X01 := '0';
        VARIABLE TD_IO8_CLK     : VitalTimingDataType;

        VARIABLE Tviol_IO9_CLK  : X01 := '0';
        VARIABLE TD_IO9_CLK     : VitalTimingDataType;

        VARIABLE Tviol_IO10_CLK : X01 := '0';
        VARIABLE TD_IO10_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO11_CLK : X01 := '0';
        VARIABLE TD_IO11_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO12_CLK : X01 := '0';
        VARIABLE TD_IO12_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO13_CLK : X01 := '0';
        VARIABLE TD_IO13_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO14_CLK : X01 := '0';
        VARIABLE TD_IO14_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO15_CLK : X01 := '0';
        VARIABLE TD_IO15_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO16_CLK : X01 := '0';
        VARIABLE TD_IO16_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO17_CLK : X01 := '0';
        VARIABLE TD_IO17_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO18_CLK : X01 := '0';
        VARIABLE TD_IO18_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO19_CLK : X01 := '0';
        VARIABLE TD_IO19_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO20_CLK : X01 := '0';
        VARIABLE TD_IO20_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO21_CLK : X01 := '0';
        VARIABLE TD_IO21_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO22_CLK : X01 := '0';
        VARIABLE TD_IO22_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO23_CLK : X01 := '0';
        VARIABLE TD_IO23_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO24_CLK : X01 := '0';
        VARIABLE TD_IO24_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO25_CLK : X01 := '0';
        VARIABLE TD_IO25_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO26_CLK : X01 := '0';
        VARIABLE TD_IO26_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO27_CLK : X01 := '0';
        VARIABLE TD_IO27_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO28_CLK : X01 := '0';
        VARIABLE TD_IO28_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO29_CLK : X01 := '0';
        VARIABLE TD_IO29_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO30_CLK : X01 := '0';
        VARIABLE TD_IO30_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO31_CLK : X01 := '0';
        VARIABLE TD_IO31_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO32_CLK : X01 := '0';
        VARIABLE TD_IO32_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO33_CLK : X01 := '0';
        VARIABLE TD_IO33_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO34_CLK : X01 := '0';
        VARIABLE TD_IO34_CLK    : VitalTimingDataType;

        VARIABLE Tviol_IO35_CLK : X01 := '0';
        VARIABLE TD_IO35_CLK    : VitalTimingDataType;

        VARIABLE Tviol_A0_CLK  : X01 := '0';
        VARIABLE TD_A0_CLK     : VitalTimingDataType;

        VARIABLE Tviol_A1_CLK  : X01 := '0';
        VARIABLE TD_A1_CLK     : VitalTimingDataType;

        VARIABLE Tviol_A2_CLK  : X01 := '0';
        VARIABLE TD_A2_CLK     : VitalTimingDataType;

        VARIABLE Tviol_A3_CLK  : X01 := '0';
        VARIABLE TD_A3_CLK     : VitalTimingDataType;

        VARIABLE Tviol_A4_CLK  : X01 := '0';
        VARIABLE TD_A4_CLK     : VitalTimingDataType;

        VARIABLE Tviol_A5_CLK  : X01 := '0';
        VARIABLE TD_A5_CLK     : VitalTimingDataType;

        VARIABLE Tviol_A6_CLK  : X01 := '0';
        VARIABLE TD_A6_CLK     : VitalTimingDataType;

        VARIABLE Tviol_A7_CLK  : X01 := '0';
        VARIABLE TD_A7_CLK     : VitalTimingDataType;

        VARIABLE Tviol_A8_CLK  : X01 := '0';
        VARIABLE TD_A8_CLK     : VitalTimingDataType;

        VARIABLE Tviol_A9_CLK  : X01 := '0';
        VARIABLE TD_A9_CLK     : VitalTimingDataType;

        VARIABLE Tviol_A10_CLK : X01 := '0';
        VARIABLE TD_A10_CLK    : VitalTimingDataType;

        VARIABLE Tviol_A11_CLK : X01 := '0';
        VARIABLE TD_A11_CLK    : VitalTimingDataType;

        VARIABLE Tviol_A12_CLK : X01 := '0';
        VARIABLE TD_A12_CLK    : VitalTimingDataType;

        VARIABLE Tviol_A13_CLK : X01 := '0';
        VARIABLE TD_A13_CLK    : VitalTimingDataType;

        VARIABLE Tviol_A14_CLK : X01 := '0';
        VARIABLE TD_A14_CLK    : VitalTimingDataType;

        VARIABLE Tviol_A15_CLK : X01 := '0';
        VARIABLE TD_A15_CLK    : VitalTimingDataType;

        VARIABLE Tviol_A16_CLK : X01 := '0';
        VARIABLE TD_A16_CLK    : VitalTimingDataType;

        VARIABLE Tviol_CLKEN_CLK : X01 := '0';
        VARIABLE TD_CLKEN_CLK    : VitalTimingDataType;

        VARIABLE Tviol_R_CLK   : X01 := '0';