mt55l128l36p.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: mt55l128l36p.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998-2008 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    98 DEC 16   Initial release
--    V1.1    R. Munden    08 AUG 14   Correct timing generic names
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    RAM
--  Technology: LVT
--  Part:       MT55L128L36P
-- 
--  Description: 128k x 36 Pipelined ZBT SRAM 
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.to_nat;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY mt55l128l36p IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A13                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A14                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A15                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A16                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO10                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO11                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO12                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO13                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO14                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO15                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO16                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO17                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO18                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO19                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO20                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO21                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO22                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO23                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO24                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO25                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO26                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO27                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO28                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO29                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO30                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO31                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO32                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO33                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO34                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO35                : VitalDelayType01 := VitalZeroDelay01;
        tipd_ZZ                  : VitalDelayType01 := VitalZeroDelay01; 
        tipd_ADV                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_R                   : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKENNeg            : VitalDelayType01 := VitalZeroDelay01;
        tipd_BW4Neg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_BW3Neg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_BW2Neg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_BW1Neg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CE1Neg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CE2Neg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CE2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_BONeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg               : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLK_IO0              : VitalDelayType01Z := UnitDelay01Z;
        tpd_OENeg_IO0            : VitalDelayType01Z := UnitDelay01Z;

        -- tpw values: pulse widths
        tpw_CLK_posedge        : VitalDelayType := UnitDelay;
        tpw_CLK_negedge        : VitalDelayType := UnitDelay;

        -- tperiod min (calculated as 1/max freq)
        tperiod_CLK_posedge    : VitalDelayType := UnitDelay;

        -- tsetup values: setup times
        tsetup_CLKENNeg_CLK     : VitalDelayType := UnitDelay;
        tsetup_A0_CLK           : VitalDelayType := UnitDelay;
        tsetup_IO0_CLK          : VitalDelayType := UnitDelay;
        tsetup_R_CLK            : VitalDelayType := UnitDelay;
        tsetup_ADV_CLK          : VitalDelayType := UnitDelay;
        tsetup_CE1Neg_CLK       : VitalDelayType := UnitDelay;
        tsetup_BW1Neg_CLK       : VitalDelayType := UnitDelay;

        -- thold values: hold times
        thold_CLKENNeg_CLK      : VitalDelayType := UnitDelay;
        thold_A0_CLK            : VitalDelayType := UnitDelay;
        thold_IO0_CLK           : VitalDelayType := UnitDelay;
        thold_R_CLK             : VitalDelayType := UnitDelay;
        thold_ADV_CLK           : VitalDelayType := UnitDelay;
        thold_CE1Neg_CLK        : VitalDelayType := UnitDelay;
        thold_BW1Neg_CLK        : VitalDelayType := UnitDelay;

        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        A0              : IN    std_logic := 'U';
        A1              : IN    std_logic := 'U';
        A2              : IN    std_logic := 'U';
        A3              : IN    std_logic := 'U';
        A4              : IN    std_logic := 'U';
        A5              : IN    std_logic := 'U';
        A6              : IN    std_logic := 'U';
        A7              : IN    std_logic := 'U';
        A8              : IN    std_logic := 'U';
        A9              : IN    std_logic := 'U';
        A10             : IN    std_logic := 'U';
        A11             : IN    std_logic := 'U';
        A12             : IN    std_logic := 'U';
        A13             : IN    std_logic := 'U';
        A14             : IN    std_logic := 'U';
        A15             : IN    std_logic := 'U';
        A16             : IN    std_logic := 'U';
        ADV             : IN    std_logic := 'U';
        R               : IN    std_logic := 'U';
        CLKENNeg        : IN    std_logic := 'U';
        BW4Neg          : IN    std_logic := 'U';
        BW3Neg          : IN    std_logic := 'U';
        BW2Neg          : IN    std_logic := 'U';
        BW1Neg          : IN    std_logic := 'U';
        CE1Neg          : IN    std_logic := 'U';
        CE2Neg          : IN    std_logic := 'U';
        CE2             : IN    std_logic := 'U';
        CLK             : IN    std_logic := 'U';
        BONeg           : IN    std_logic := 'U';
        OENeg           : IN    std_logic := 'U';
        IO0             : INOUT std_logic := 'Z';
        IO1             : INOUT std_logic := 'Z';
        IO2             : INOUT std_logic := 'Z';
        IO3             : INOUT std_logic := 'Z';
        IO4             : INOUT std_logic := 'Z';
        IO5             : INOUT std_logic := 'Z';
        IO6             : INOUT std_logic := 'Z';
        IO7             : INOUT std_logic := 'Z';
        IO8             : INOUT std_logic := 'Z';
        IO9             : INOUT std_logic := 'Z';
        IO10            : INOUT std_logic := 'Z';
        IO11            : INOUT std_logic := 'Z';
        IO12            : INOUT std_logic := 'Z';
        IO13            : INOUT std_logic := 'Z';
        IO14            : INOUT std_logic := 'Z';
        IO15            : INOUT std_logic := 'Z';
        IO16            : INOUT std_logic := 'Z';
        IO17            : INOUT std_logic := 'Z';
        IO18            : INOUT std_logic := 'Z';
        IO19            : INOUT std_logic := 'Z';
        IO20            : INOUT std_logic := 'Z';
        IO21            : INOUT std_logic := 'Z';
        IO22            : INOUT std_logic := 'Z';
        IO23            : INOUT std_logic := 'Z';
        IO24            : INOUT std_logic := 'Z';
        IO25            : INOUT std_logic := 'Z';
        IO26            : INOUT std_logic := 'Z';
        IO27            : INOUT std_logic := 'Z';
        IO28            : INOUT std_logic := 'Z';
        IO29            : INOUT std_logic := 'Z';
        IO30            : INOUT std_logic := 'Z';
        IO31            : INOUT std_logic := 'Z';
        IO32            : INOUT std_logic := 'Z';
        IO33            : INOUT std_logic := 'Z';
        IO34            : INOUT std_logic := 'Z';
        IO35            : INOUT std_logic := 'Z';
        ZZ              : IN std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of mt55l128l36p : ENTITY IS TRUE;
END mt55l128l36p;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of mt55l128l36p IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A0_ipd              : std_ulogic := 'X';
    SIGNAL A1_ipd              : std_ulogic := 'X';
    SIGNAL A2_ipd              : std_ulogic := 'X';
    SIGNAL A3_ipd              : std_ulogic := 'X';
    SIGNAL A4_ipd              : std_ulogic := 'X';
    SIGNAL A5_ipd              : std_ulogic := 'X';
    SIGNAL A6_ipd              : std_ulogic := 'X';
    SIGNAL A7_ipd              : std_ulogic := 'X';
    SIGNAL A8_ipd              : std_ulogic := 'X';
    SIGNAL A9_ipd              : std_ulogic := 'X';
    SIGNAL A10_ipd             : std_ulogic := 'X';
    SIGNAL A11_ipd             : std_ulogic := 'X';
    SIGNAL A12_ipd             : std_ulogic := 'X';
    SIGNAL A13_ipd             : std_ulogic := 'X';
    SIGNAL A14_ipd             : std_ulogic := 'X';
    SIGNAL A15_ipd             : std_ulogic := 'X';
    SIGNAL A16_ipd             : std_ulogic := 'X';
    SIGNAL IO0_ipd             : std_ulogic := 'X';
    SIGNAL IO1_ipd             : std_ulogic := 'X';
    SIGNAL IO2_ipd             : std_ulogic := 'X';
    SIGNAL IO3_ipd             : std_ulogic := 'X';
    SIGNAL IO4_ipd             : std_ulogic := 'X';
    SIGNAL IO5_ipd             : std_ulogic := 'X';
    SIGNAL IO6_ipd             : std_ulogic := 'X';
    SIGNAL IO7_ipd             : std_ulogic := 'X';
    SIGNAL IO8_ipd             : std_ulogic := 'X';
    SIGNAL IO9_ipd             : std_ulogic := 'X';
    SIGNAL IO10_ipd            : std_ulogic := 'X';
    SIGNAL IO11_ipd            : std_ulogic := 'X';
    SIGNAL IO12_ipd            : std_ulogic := 'X';
    SIGNAL IO13_ipd            : std_ulogic := 'X';
    SIGNAL IO14_ipd            : std_ulogic := 'X';
    SIGNAL IO15_ipd            : std_ulogic := 'X';
    SIGNAL IO16_ipd            : std_ulogic := 'X';
    SIGNAL IO17_ipd            : std_ulogic := 'X';
    SIGNAL IO18_ipd            : std_ulogic := 'X';
    SIGNAL IO19_ipd            : std_ulogic := 'X';
    SIGNAL IO20_ipd            : std_ulogic := 'X';
    SIGNAL IO21_ipd            : std_ulogic := 'X';
    SIGNAL IO22_ipd            : std_ulogic := 'X';
    SIGNAL IO23_ipd            : std_ulogic := 'X';
    SIGNAL IO24_ipd            : std_ulogic := 'X';
    SIGNAL IO25_ipd            : std_ulogic := 'X';
    SIGNAL IO26_ipd            : std_ulogic := 'X';
    SIGNAL IO27_ipd            : std_ulogic := 'X';
    SIGNAL IO28_ipd            : std_ulogic := 'X';
    SIGNAL IO29_ipd            : std_ulogic := 'X';
    SIGNAL IO30_ipd            : std_ulogic := 'X';
    SIGNAL IO31_ipd            : std_ulogic := 'X';
    SIGNAL IO32_ipd            : std_ulogic := 'X';
    SIGNAL IO33_ipd            : std_ulogic := 'X';
    SIGNAL IO34_ipd            : std_ulogic := 'X';
    SIGNAL IO35_ipd            : std_ulogic := 'X';
    SIGNAL ADV_ipd             : std_ulogic := 'X';
    SIGNAL R_ipd               : std_ulogic := 'X';
    SIGNAL CLKENNeg_ipd        : std_ulogic := 'X';
    SIGNAL BW4Neg_ipd          : std_ulogic := 'X';
    SIGNAL BW3Neg_ipd          : std_ulogic := 'X';
    SIGNAL BW2Neg_ipd          : std_ulogic := 'X';
    SIGNAL BW1Neg_ipd          : std_ulogic := 'X';
    SIGNAL CE1Neg_ipd          : std_ulogic := 'X';
    SIGNAL CE2Neg_ipd          : std_ulogic := 'X';
    SIGNAL CE2_ipd             : std_ulogic := 'X';
    SIGNAL CLK_ipd             : std_ulogic := 'X';
    SIGNAL BONeg_ipd           : std_ulogic := 'X';
    SIGNAL OENeg_ipd           : std_ulogic := 'X';
    SIGNAL ZZ_ipd              : std_ulogic := 'X';
    SIGNAL ADV_nwv             : std_ulogic := 'X';