📄 idt703399prf.vhd
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VARIABLE DataL1tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataL0tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataR1tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataR0tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataTempL1 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempL0 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempR1 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempR0 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataL1 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataL0 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataR1 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataR0 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE LocationL : NATURAL RANGE 0 TO TotalLOC := 0; VARIABLE LocationR : NATURAL RANGE 0 TO TotalLOC := 0; VARIABLE LastLocL : NATURAL RANGE 0 TO TotalLOC := 0; VARIABLE LastLocR : NATURAL RANGE 0 TO TotalLOC := 0; VARIABLE MemData1 : MemStore; VARIABLE MemData0 : MemStore; VARIABLE LatencyL : BOOLEAN; VARIABLE LatencyR : BOOLEAN; -- No Weak Values Variables VARIABLE CE0LNeg_nwv : UX01 := 'U'; VARIABLE CE0RNeg_nwv : UX01 := 'U'; VARIABLE CE1L_nwv : UX01 := 'U'; VARIABLE CE1R_nwv : UX01 := 'U'; VARIABLE CE0LNeg_reg : UX01 := 'U'; VARIABLE CE0RNeg_reg : UX01 := 'U'; VARIABLE CE1L_reg : UX01 := 'U'; VARIABLE CE1R_reg : UX01 := 'U'; VARIABLE RWR_nwv : UX01 := 'U'; VARIABLE RWL_nwv : UX01 := 'U'; VARIABLE ADSLNeg_nwv : UX01 := 'U'; VARIABLE ADSRNeg_nwv : UX01 := 'U'; VARIABLE OELNeg_nwv : UX01 := 'U'; VARIABLE OERNeg_nwv : UX01 := 'U'; VARIABLE BE1LNeg_nwv : UX01 := 'U'; VARIABLE BE0LNeg_nwv : UX01 := 'U'; VARIABLE BE1RNeg_nwv : UX01 := 'U'; VARIABLE BE0RNeg_nwv : UX01 := 'U'; VARIABLE BE1LNeg_reg : UX01 := 'U'; VARIABLE BE0LNeg_reg : UX01 := 'U'; VARIABLE BE1RNeg_reg : UX01 := 'U'; VARIABLE BE0RNeg_reg : UX01 := 'U'; VARIABLE REPEATLNeg_nwv : UX01 := 'U'; VARIABLE REPEATRNeg_nwv : UX01 := 'U'; VARIABLE CNTENLNeg_nwv : UX01 := 'U'; VARIABLE CNTENRNeg_nwv : UX01 := 'U'; BEGIN CE0LNeg_nwv := To_UX01 (s => CE0LNegIn); CE0RNeg_nwv := To_UX01 (s => CE0RNegIn); CE1L_nwv := To_UX01 (s => CE1LIn); CE1R_nwv := To_UX01 (s => CE1RIn); RWL_nwv := To_UX01 (s => RWLIn); RWR_nwv := To_UX01 (s => RWRIn); ADSLNeg_nwv := To_UX01 (s => ADSLNegIn); ADSRNeg_nwv := To_UX01 (s => ADSRNegIn); OELNeg_nwv := To_UX01 (s => OELNegIn); OERNeg_nwv := To_UX01 (s => OERNegIn); BE1LNeg_nwv := To_UX01 (s => BE1LNegIn); BE0LNeg_nwv := To_UX01 (s => BE0LNegIn); BE1RNeg_nwv := To_UX01 (s => BE1RNegIn); BE0RNeg_nwv := To_UX01 (s => BE0RNegIn); REPEATLNeg_nwv := To_UX01 (s => REPEATLNegIn); REPEATRNeg_nwv := To_UX01 (s => REPEATRNegIn); CNTENLNeg_nwv := To_UX01 (s => CNTENLNegIn); CNTENRNeg_nwv := To_UX01 (s => CNTENRNegIn); -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_AL0_CLKL, SetupLow => tsetup_AL0_CLKL, HoldHigh => thold_AL0_CLKL, HoldLow => thold_AL0_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ALIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ALIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_AL0_CLKL, SetupLow => tsetup_AL0_CLKL, HoldHigh => thold_AL0_CLKL, HoldLow => thold_AL0_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ARIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ARIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => CE0LNegIn, TestSignalName => "CE0LNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE0LNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0LNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => CE0RNegIn, TestSignalName => "CE0RNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE0RNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0RNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => CE1LIn, TestSignalName => "CE1L", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE1LIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1LIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => CE1RIn, TestSignalName => "CE1R", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE1RIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1RIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => RWLIn, TestSignalName => "RWL", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_RWL_CLKL, SetupLow => tsetup_RWL_CLKL, HoldHigh => thold_RWL_CLKL, HoldLow => thold_RWL_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RWLIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWLIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => RWRIn, TestSignalName => "RWR", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_RWL_CLKL, SetupLow => tsetup_RWL_CLKL, HoldHigh => thold_RWL_CLKL, HoldLow => thold_RWL_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RWRIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWRIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => IOL1In, TestSignalName => "IOL1", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1' AND RWL_nwv = '0' AND BE1LNeg_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOL1In_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOL1In_CLKLIn ); VitalSetupHoldCheck ( TestSignal => IOL0In, TestSignalName => "IOL0", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1' AND RWL_nwv = '0' AND BE0LNeg_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOL0In_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOL0In_CLKLIn ); VitalSetupHoldCheck ( TestSignal => IOR1In, TestSignalName => "IOR1", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'
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