idt703399prf.vhd

vhdl cod for ram.For sp3e

            OPTLIn       : IN    std_ulogic := 'U';
            RWLIn        : IN    std_ulogic := 'U';
            RWRIn        : IN    std_ulogic := 'U';
            OELNegIn     : IN    std_ulogic := 'U';
            OERNegIn     : IN    std_ulogic := 'U';
            BE1LNegIn    : IN    std_ulogic := 'U';
            BE0LNegIn    : IN    std_ulogic := 'U';
            BE1RNegIn    : IN    std_ulogic := 'U';
            BE0RNegIn    : IN    std_ulogic := 'U';
            CE0LNegIn    : IN    std_ulogic := 'U';
            CE0RNegIn    : IN    std_ulogic := 'U';
            CE1LIn       : IN    std_ulogic := 'U';
            CE1RIn       : IN    std_ulogic := 'U';
            CLKLIn       : IN    std_ulogic := 'U';
            CLKRIn       : IN    std_ulogic := 'U';
            REPEATLNegIn : IN    std_ulogic := 'U';
            REPEATRNegIn : IN    std_ulogic := 'U';
            CNTENRNegIn  : IN    std_ulogic := 'U';
            CNTENLNegIn  : IN    std_ulogic := 'U';
            ADSRNegIn    : IN    std_ulogic := 'U';
            ADSLNegIn    : IN    std_ulogic := 'U';
            PIPERIn      : IN    std_ulogic := '1';
            PIPELIn      : IN    std_ulogic := '1'
        );
        PORT MAP (
            ALIn(0) =>  AL0_ipd,
            ALIn(1) =>  AL1_ipd,
            ALIn(2) =>  AL2_ipd,
            ALIn(3) =>  AL3_ipd,
            ALIn(4) =>  AL4_ipd,
            ALIn(5) =>  AL5_ipd,
            ALIn(6) =>  AL6_ipd,
            ALIn(7) =>  AL7_ipd,
            ALIn(8) =>  AL8_ipd,
            ALIn(9) =>  AL9_ipd,
            ALIn(10) =>  AL10_ipd,
            ALIn(11) =>  AL11_ipd,
            ALIn(12) =>  AL12_ipd,
            ALIn(13) =>  AL13_ipd,
            ALIn(14) =>  AL14_ipd,
            ALIn(15) =>  AL15_ipd,
            ALIn(16) =>  AL16_ipd,
            ARIn(0) =>  AR0_ipd,
            ARIn(1) =>  AR1_ipd,
            ARIn(2) =>  AR2_ipd,
            ARIn(3) =>  AR3_ipd,
            ARIn(4) =>  AR4_ipd,
            ARIn(5) =>  AR5_ipd,
            ARIn(6) =>  AR6_ipd,
            ARIn(7) =>  AR7_ipd,
            ARIn(8) =>  AR8_ipd,
            ARIn(9) =>  AR9_ipd,
            ARIn(10) =>  AR10_ipd,
            ARIn(11) =>  AR11_ipd,
            ARIn(12) =>  AR12_ipd,
            ARIn(13) =>  AR13_ipd,
            ARIn(14) =>  AR14_ipd,
            ARIn(15) =>  AR15_ipd,
            ARIn(16) =>  AR16_ipd,
            IOL0In(0) => IOL0_ipd,
            IOL0In(1) => IOL1_ipd,
            IOL0In(2) => IOL2_ipd,
            IOL0In(3) => IOL3_ipd,
            IOL0In(4) => IOL4_ipd,
            IOL0In(5) => IOL5_ipd,
            IOL0In(6) => IOL6_ipd,
            IOL0In(7) => IOL7_ipd,
            IOL0In(8) => IOL8_ipd,
            IOL1In(0) => IOL9_ipd,
            IOL1In(1) => IOL10_ipd,
            IOL1In(2) => IOL11_ipd,
            IOL1In(3) => IOL12_ipd,
            IOL1In(4) => IOL13_ipd,
            IOL1In(5) => IOL14_ipd,
            IOL1In(6) => IOL15_ipd,
            IOL1In(7) => IOL16_ipd,
            IOL1In(8) => IOL17_ipd,
            IOR0In(0) => IOR0_ipd,
            IOR0In(1) => IOR1_ipd,
            IOR0In(2) => IOR2_ipd,
            IOR0In(3) => IOR3_ipd,
            IOR0In(4) => IOR4_ipd,
            IOR0In(5) => IOR5_ipd,
            IOR0In(6) => IOR6_ipd,
            IOR0In(7) => IOR7_ipd,
            IOR0In(8) => IOR8_ipd,
            IOR1In(0) => IOR9_ipd,
            IOR1In(1) => IOR10_ipd,
            IOR1In(2) => IOR11_ipd,
            IOR1In(3) => IOR12_ipd,
            IOR1In(4) => IOR13_ipd,
            IOR1In(5) => IOR14_ipd,
            IOR1In(6) => IOR15_ipd,
            IOR1In(7) => IOR16_ipd,
            IOR1In(8) => IOR17_ipd,
            IOL0Out(0) => IOL0,
            IOL0Out(1) => IOL1,
            IOL0Out(2) => IOL2,
            IOL0Out(3) => IOL3,
            IOL0Out(4) => IOL4,
            IOL0Out(5) => IOL5,
            IOL0Out(6) => IOL6,
            IOL0Out(7) => IOL7,
            IOL0Out(8) => IOL8,
            IOL1Out(0) => IOL9,
            IOL1Out(1) => IOL10,
            IOL1Out(2) => IOL11,
            IOL1Out(3) => IOL12,
            IOL1Out(4) => IOL13,
            IOL1Out(5) => IOL14,
            IOL1Out(6) => IOL15,
            IOL1Out(7) => IOL16,
            IOL1Out(8) => IOL17,
            IOR0Out(0) => IOR0,
            IOR0Out(1) => IOR1,
            IOR0Out(2) => IOR2,
            IOR0Out(3) => IOR3,
            IOR0Out(4) => IOR4,
            IOR0Out(5) => IOR5,
            IOR0Out(6) => IOR6,
            IOR0Out(7) => IOR7,
            IOR0Out(8) => IOR8,
            IOR1Out(0) => IOR9,
            IOR1Out(1) => IOR10,
            IOR1Out(2) => IOR11,
            IOR1Out(3) => IOR12,
            IOR1Out(4) => IOR13,
            IOR1Out(5) => IOR14,
            IOR1Out(6) => IOR15,
            IOR1Out(7) => IOR16,
            IOR1Out(8) => IOR17,
            OPTRIn    => OPTR_ipd,
            OPTLIn    => OPTL_ipd,
            RWLIn     => RWL_ipd,
            RWRIn     => RWR_ipd,
            OELNegIn  => OELNeg_ipd,
            OERNegIn  => OERNeg_ipd,
            BE1RNegIn  => BE1RNeg_ipd,
            BE0RNegIn  => BE0RNeg_ipd,
            BE1LNegIn  => BE1LNeg_ipd,
            BE0LNegIn  => BE0LNeg_ipd,
            CE0LNegIn  => CE0LNeg_ipd,
            CE0RNegIn  => CE0RNeg_ipd,
            CE1LIn  => CE1L_ipd,
            CE1RIn  => CE1R_ipd,
            CLKLIn  => CLKL_ipd,
            CLKRIn  => CLKR_ipd,
            REPEATLNegIn  => REPEATLNeg_ipd,
            REPEATRNegIn  => REPEATRNeg_ipd,
            CNTENRNegIn  => CNTENRNeg_ipd,
            CNTENLNegIn  => CNTENLNeg_ipd,
            ADSRNegIn  => ADSRNeg_ipd,
            ADSLNegIn  => ADSLNeg_ipd
        );

        SIGNAL IOL1_zd      : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL IOL0_zd      : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL IOR1_zd      : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL IOR0_zd      : std_logic_vector(HiDbit DOWNTO 0);

    BEGIN

        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Memory : PROCESS (OELNegIn, OERNegIn, RWLIn, RWRIn, CE0LNegIn,
                          CE0RNegIn, ALIn, ARIn, IOL0In, IOR0In, CE1LIn, CE1RIn,
                          CLKLIn, CLKRIn, REPEATLNegIn, REPEATRNegIn,
                          CNTENRNegIn, CNTENLNegIn, ADSRNegIn, ADSLNegIn,
                          PIPERIn, PIPELIn, IOL1In, IOR1In, BE1RNegIn,
                          BE1LNegIn, BE0RNegIn, BE0LNegIn)

            -- Timing Check Variables
            VARIABLE Tviol_ALIn_CLKLIn         : X01 := '0';
            VARIABLE TD_ALIn_CLKLIn            : VitalTimingDataType;

            VARIABLE Tviol_ARIn_CLKRIn         : X01 := '0';
            VARIABLE TD_ARIn_CLKRIn            : VitalTimingDataType;

            VARIABLE Tviol_CE0LNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_CE0LNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_CE0RNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_CE0RNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_CE1LIn_CLKLIn       :  X01 := '0';
            VARIABLE TD_CE1LIn_CLKLIn          : VitalTimingDataType;

            VARIABLE Tviol_CE1RIn_CLKRIn       :  X01 := '0';
            VARIABLE TD_CE1RIn_CLKRIn          : VitalTimingDataType;

            VARIABLE Tviol_RWLIn_CLKLIn        : X01 := '0';
            VARIABLE TD_RWLIn_CLKLIn           : VitalTimingDataType;

            VARIABLE Tviol_RWRIn_CLKRIn        : X01 := '0';
            VARIABLE TD_RWRIn_CLKRIn           : VitalTimingDataType;

            VARIABLE Tviol_IOL1In_CLKLIn       : X01 := '0';
            VARIABLE TD_IOL1In_CLKLIn          : VitalTimingDataType;

            VARIABLE Tviol_IOL0In_CLKLIn       : X01 := '0';
            VARIABLE TD_IOL0In_CLKLIn          : VitalTimingDataType;

            VARIABLE Tviol_IOR1In_CLKRIn       : X01 := '0';
            VARIABLE TD_IOR1In_CLKRIn          : VitalTimingDataType;

            VARIABLE Tviol_IOR0In_CLKRIn       : X01 := '0';
            VARIABLE TD_IOR0In_CLKRIn          : VitalTimingDataType;

            VARIABLE Tviol_BE1RNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_BE1RNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_BE0RNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_BE0RNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_BE1LNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_BE1LNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_BE0LNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_BE0LNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_ADSLNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_ADSLNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_ADSRNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_ADSRNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_CNTENLNegIn_CLKLIn  :  X01 := '0';
            VARIABLE TD_CNTENLNegIn_CLKLIn     : VitalTimingDataType;

            VARIABLE Tviol_CNTENRNegIn_CLKRIn  :  X01 := '0';
            VARIABLE TD_CNTENRNegIn_CLKRIn     : VitalTimingDataType;

            VARIABLE Tviol_REPEATLNegIn_CLKLIn :  X01 := '0';
            VARIABLE TD_REPEATLNegIn_CLKLIn    : VitalTimingDataType;

            VARIABLE Tviol_REPEATRNegIn_CLKRIn :  X01 := '0';
            VARIABLE TD_REPEATRNegIn_CLKRIn    : VitalTimingDataType;

            VARIABLE Pviol_CLKLIn1             :  X01 := '0';
            VARIABLE TD_CLKLIn1    : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_CLKRIn1             :  X01 := '0';
            VARIABLE TD_CLKRIn1    : VitalPeriodDataType := VitalPeriodDataInit;

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
                             RANGE  -2 TO MaxData;

            VARIABLE DataL1Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataL0Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataR1Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataR0Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');