idt70t3509m.vhd

vhdl cod for ram.For sp3e

        SIGNAL CELReg      : std_logic;  -- Registrated CE signal...
        SIGNAL CERReg      : std_logic;  -- Registrated CE signal...
        SIGNAL BEL0NegPipe : std_logic;  -- Pipeline BE0Neg...
        SIGNAL BER0NegPipe : std_logic;  -- Pipeline BE0Neg...
        SIGNAL BEL1NegPipe : std_logic;  -- Pipeline BE0Neg...
        SIGNAL BER1NegPipe : std_logic;  -- Pipeline BE0Neg...
        SIGNAL BEL2NegPipe : std_logic;  -- Pipeline BE0Neg...
        SIGNAL BER2NegPipe : std_logic;  -- Pipeline BE0Neg...
        SIGNAL BEL3NegPipe : std_logic;  -- Pipeline BE0Neg...
        SIGNAL BER3NegPipe : std_logic;  -- Pipeline BE0Neg...
        SIGNAL BEL0Mux     : std_logic;  -- BENeg from multiplexer...
        SIGNAL BER0Mux     : std_logic;  -- BENeg from multiplexer...
        SIGNAL BEL1Mux     : std_logic;  -- BENeg from multiplexer...
        SIGNAL BER1Mux     : std_logic;  -- BENeg from multiplexer...
        SIGNAL BEL2Mux     : std_logic;  -- BENeg from multiplexer...
        SIGNAL BER2Mux     : std_logic;  -- BENeg from multiplexer...
        SIGNAL BEL3Mux     : std_logic;  -- BENeg from multiplexer...
        SIGNAL BER3Mux     : std_logic;  -- BENeg from multiplexer...
        SIGNAL CELMuxIn    : std_logic;  -- Input to mux for CE
        SIGNAL CERMuxIn    : std_logic;  -- Input to mux for CE
        SIGNAL CELMux      : std_logic;  -- CE from mux...
        SIGNAL CERMux      : std_logic;  -- CE from mux...
        SIGNAL MemBEL0     : std_logic;  -- BE for Memory array
        SIGNAL MemBER0     : std_logic;  -- BE for Memory array
        SIGNAL MemBEL1     : std_logic;  -- BE for Memory array
        SIGNAL MemBER1     : std_logic;  -- BE for Memory array
        SIGNAL MemBEL2     : std_logic;  -- BE for Memory array
        SIGNAL MemBER2     : std_logic;  -- BE for Memory array
        SIGNAL MemBEL3     : std_logic;  -- BE for Memory array
        SIGNAL MemBER3     : std_logic;  -- BE for Memory array
        SIGNAL DoutL0Sel   : std_logic;  -- Output selection signal
        SIGNAL DoutR0Sel   : std_logic;  -- Output selection signal
        SIGNAL DoutL1Sel   : std_logic;  -- Output selection signal
        SIGNAL DoutR1Sel   : std_logic;  -- Output selection signal
        SIGNAL DoutL2Sel   : std_logic;  -- Output selection signal
        SIGNAL DoutR2Sel   : std_logic;  -- Output selection signal
        SIGNAL DoutL3Sel   : std_logic;  -- Output selection signal
        SIGNAL DoutR3Sel   : std_logic;  -- Output selection signal
        SIGNAL MemAddrInL  : natural RANGE 0 TO MemSize;
        SIGNAL MemAddrInR  : natural RANGE 0 TO MemSize;
        -- Sleep internal signals...
        SIGNAL ZZR_int     : STD_LOGIC := '0';
        SIGNAL ZZL_int     : STD_LOGIC := '0';
        -- Registrated BELInNeg signal
        SIGNAL BELNegReg   : std_logic_vector(3 DOWNTO 0);
        -- Pipeline BELNegReg
        SIGNAL BELNegPipe  : std_logic_vector(3 DOWNTO 0);
        -- Registrated BERInNeg signal
        SIGNAL BERNegReg   : std_logic_vector(3 DOWNTO 0);
        -- Pipeline BERNegReg
        SIGNAL BERNegPipe  : std_logic_vector(3 DOWNTO 0);
        -- Registrated Memory otput signals
        SIGNAL MemOutLReg  : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL MemOutRReg  : std_logic_vector(HiDbit DOWNTO 0);
        -- Memory output
        SIGNAL MemOutL     : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL MemOutR     : std_logic_vector(HiDbit DOWNTO 0);
        -- Outputs from buffers
        SIGNAL DOL_zd      : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL DOR_zd      : std_logic_vector(HiDbit DOWNTO 0);
        -- Input signal registrated
        SIGNAL MemInRegL   : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL MemInRegR   : std_logic_vector(HiDbit DOWNTO 0);
        -- Signals needed for Interrupt signal delay
        SIGNAL INTLNeg_zd  : STD_LOGIC := '1';
        SIGNAL INTRNeg_zd  : STD_LOGIC := '1';

        SUBTYPE std_logic_vector9 IS std_logic_vector(8 DOWNTO 0);
        ALIAS outLZD0     : std_logic_vector9 IS DOL_zd(8 DOWNTO 0);
        ALIAS outRZD0     : std_logic_vector9 IS DOR_zd(8 DOWNTO 0);
        ALIAS outLZD1     : std_logic_vector9 IS DOL_zd(17 DOWNTO 9);
        ALIAS outRZD1     : std_logic_vector9 IS DOR_zd(17 DOWNTO 9);
        ALIAS outLZD2     : std_logic_vector9 IS DOL_zd(26 DOWNTO 18);
        ALIAS outRZD2     : std_logic_vector9 IS DOR_zd(26 DOWNTO 18);
        ALIAS outLZD3     : std_logic_vector9 IS DOL_zd(35 DOWNTO 27);
        ALIAS outRZD3     : std_logic_vector9 IS DOR_zd(35 DOWNTO 27);
        ALIAS MemOutL0    : std_logic_vector9 IS MemOutL(8 DOWNTO 0);
        ALIAS MemOutR0    : std_logic_vector9 IS MemOutR(8 DOWNTO 0);
        ALIAS MemOutL1    : std_logic_vector9 IS MemOutL(17 DOWNTO 9);
        ALIAS MemOutR1    : std_logic_vector9 IS MemOutR(17 DOWNTO 9);
        ALIAS MemOutL2    : std_logic_vector9 IS MemOutL(26 DOWNTO 18);
        ALIAS MemOutR2    : std_logic_vector9 IS MemOutR(26 DOWNTO 18);
        ALIAS MemOutL3    : std_logic_vector9 IS MemOutL(35 DOWNTO 27);
        ALIAS MemOutR3    : std_logic_vector9 IS MemOutR(35 DOWNTO 27);
        ALIAS MemOutL0Reg : std_logic_vector9 IS MemOutLReg(8 DOWNTO 0);
        ALIAS MemOutR0Reg : std_logic_vector9 IS MemOutRReg(8 DOWNTO 0);
        ALIAS MemOutL1Reg : std_logic_vector9 IS MemOutLReg(17 DOWNTO 9);
        ALIAS MemOutR1Reg : std_logic_vector9 IS MemOutRReg(17 DOWNTO 9);
        ALIAS MemOutL2Reg : std_logic_vector9 IS MemOutLReg(26 DOWNTO 18);
        ALIAS MemOutR2Reg : std_logic_vector9 IS MemOutRReg(26 DOWNTO 18);
        ALIAS MemOutL3Reg : std_logic_vector9 IS MemOutLReg(35 DOWNTO 27);
        ALIAS MemOutR3Reg : std_logic_vector9 IS MemOutRReg(35 DOWNTO 27);

        TYPE mem_type IS ARRAY(0 TO MemSize) OF integer RANGE -2 TO MaxData;
        SHARED VARIABLE MemDataA : mem_type := (OTHERS => -2);
        SHARED VARIABLE MemDataB : mem_type := (OTHERS => -2);
        SHARED VARIABLE MemDataC : mem_type := (OTHERS => -2);
        SHARED VARIABLE MemDataD : mem_type := (OTHERS => -2);

        SIGNAL writeL  : std_logic := '0';
        SIGNAL writeR  : std_logic := '0';
        SIGNAL readL   : std_logic := '0';
        SIGNAL readR   : std_logic := '0';
        SIGNAL chng_lp : STD_LOGIC := '0';
        SIGNAL chng_rp : STD_LOGIC := '0';

        TYPE mem_state IS (desel, read, write, collision);
        SHARED VARIABLE stateL : mem_state;
        SHARED VARIABLE stateR : mem_state;

        SIGNAL Viol : X01 := '0';

    BEGIN
        --------------------------------------------------------------------
        -- Timing Check Section
        --------------------------------------------------------------------
        VITALTimingCheck : PROCESS (CLKL, CLKR, ALIn, ARIn, CE0LNeg, CE0RNeg,
                                    CE1R,CE1L,
                                    BELInNeg, BERInNeg, RWL, RWR, IOLIn, IORIn,
                                    ADSLNeg, ADSRNeg, CNTENLNeg, CNTENRNeg,
                                    REPEATLNeg, REPEATRNeg,PLFTR,PLFTL ) IS

            --Setup/Hold checks variables
            VARIABLE TD_AL0_CLKL           : VitalTimingDataType;
            VARIABLE Tviol_AL0_CLKL        : X01 := '0';
            VARIABLE TD_AR0_CLKR           : VitalTimingDataType;
            VARIABLE Tviol_AR0_CLKR        : X01 := '0';
            VARIABLE TD_CE0LNeg_CLKL       : VitalTimingDataType;
            VARIABLE Tviol_CE0LNeg_CLKL    : X01 := '0';
            VARIABLE TD_CE0RNeg_CLKR       : VitalTimingDataType;
            VARIABLE Tviol_CE0RNeg_CLKR    : X01 := '0';
            VARIABLE TD_CE1L_CLKL          : VitalTimingDataType;
            VARIABLE Tviol_CE1L_CLKL       : X01 := '0';
            VARIABLE TD_CE1R_CLKR          : VitalTimingDataType;
            VARIABLE Tviol_CE1R_CLKR       : X01 := '0';
            VARIABLE TD_BEL0Neg_CLKL       : VitalTimingDataType;
            VARIABLE Tviol_BEL0Neg_CLKL    : X01 := '0';
            VARIABLE TD_BER0Neg_CLKR       : VitalTimingDataType;
            VARIABLE Tviol_BER0Neg_CLKR    : X01 := '0';
            VARIABLE TD_RWL_CLKL           : VitalTimingDataType;
            VARIABLE Tviol_RWL_CLKL        : X01 := '0';
            VARIABLE TD_RWR_CLKR           : VitalTimingDataType;
            VARIABLE Tviol_RWR_CLKR        : X01 := '0';
            VARIABLE TD_IOL0_CLKL          : VitalTimingDataType;
            VARIABLE Tviol_IOL0_CLKL       : X01 := '0';
            VARIABLE TD_IOR0_CLKR          : VitalTimingDataType;
            VARIABLE Tviol_IOR0_CLKR       : X01 := '0';
            VARIABLE TD_ADSLNeg_CLKL       : VitalTimingDataType;
            VARIABLE Tviol_ADSLNeg_CLKL    : X01 := '0';
            VARIABLE TD_ADSRNeg_CLKR       : VitalTimingDataType;
            VARIABLE Tviol_ADSRNeg_CLKR    : X01 := '0';
            VARIABLE TD_CNTENLNeg_CLKL     : VitalTimingDataType;
            VARIABLE Tviol_CNTENLNeg_CLKL  : X01 := '0';
            VARIABLE TD_CNTENRNeg_CLKR     : VitalTimingDataType;
            VARIABLE Tviol_CNTENRNeg_CLKR  : X01 := '0';
            VARIABLE TD_REPEATLNeg_CLKL    : VitalTimingDataType;
            VARIABLE Tviol_REPEATLNeg_CLKL : X01 := '0';
            VARIABLE TD_REPEATRNeg_CLKR    : VitalTimingDataType;
            VARIABLE Tviol_REPEATRNeg_CLKR : X01 := '0';

            -- Pulse Width and Period Check Variables
            VARIABLE Pviol_CLKL_PIPELINE_EQ_1 : X01                 := '0';
            VARIABLE PD_CLKL_PIPELINE_EQ_1    : VitalPeriodDataType :=
                VitalPeriodDataInit;
            VARIABLE Pviol_CLKL_NOPIPELINE_EQ_1 : X01                 := '0';
            VARIABLE PD_CLKL_NOPIPELINE_EQ_1    : VitalPeriodDataType :=
                VitalPeriodDataInit;
            VARIABLE Pviol_CLKR_PIPELINE_EQ_1 : X01                 := '0';
            VARIABLE PD_CLKR_PIPELINE_EQ_1    : VitalPeriodDataType :=
                VitalPeriodDataInit;
            VARIABLE Pviol_CLKR_NOPIPELINE_EQ_1 : X01                 := '0';
            VARIABLE PD_CLKR_NOPIPELINE_EQ_1    : VitalPeriodDataType :=
                VitalPeriodDataInit;
            VARIABLE Violation : X01 := '0';

        BEGIN
            --------------------------------
            -- Timing Check Section
            --------------------------------
            IF TimingChecksOn THEN
                -- CLKL pulse ( low&high ) width and period check,
                -- WHEN PIPELINE
                VitalPeriodPulseCheck (
                    TestSignal      => CLKL,
                    TestSignalName  => "CLKL",
                    Period          => tperiod_CLKL_PIPELINE_EQ_1,
                    PulseWidthHigh  => tpw_CLKL_PIPELINE_EQ_1_posedge,
                    PulseWidthLow   => tpw_CLKL_PIPELINE_EQ_1_negedge,
                    CheckEnabled    => PLFTL = '1',
                    HeaderMsg       => InstancePath & partID,
                    PeriodData      => PD_CLKL_PIPELINE_EQ_1,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Pviol_CLKL_PIPELINE_EQ_1);
                -- CLKL pulse ( low&high ) width and period check,
                -- WHEN NOPIPELINE
                VitalPeriodPulseCheck (
                    TestSignal      => CLKL,
                    TestSignalName  => "CLKL",
                    Period          => tperiod_CLKL_NOPIPELINE_EQ_1,
                    PulseWidthHigh  => tpw_CLKL_NOPIPELINE_EQ_1_posedge,
                    PulseWidthLow   => tpw_CLKL_NOPIPELINE_EQ_1_negedge,
                    CheckEnabled    => PLFTL = '0',
                    HeaderMsg       => InstancePath & partID,
                    PeriodData      => PD_CLKL_NOPIPELINE_EQ_1,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Pviol_CLKL_NOPIPELINE_EQ_1);
                -- CLKR pulse ( low&high ) width and period check,
                -- WHEN PIPELINE
                VitalPeriodPulseCheck (
                    TestSignal      => CLKR,
                    TestSignalName  => "CLKR",
                    Period          => tperiod_CLKR_PIPELINE_EQ_1,
                    PulseWidthHigh  => tpw_CLKR_PIPELINE_EQ_1_posedge,
                    PulseWidthLow   => tpw_CLKR_PIPELINE_EQ_1_negedge,
                    CheckEnabled    => PLFTR = '1',
                    HeaderMsg       => InstancePath & partID,
                    PeriodData      => PD_CLKR_PIPELINE_EQ_1,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Pviol_CLKR_PIPELINE_EQ_1);
                -- CLKR pulse ( low&high ) width and period check,
                -- WHEN NOPIPELINE
                VitalPeriodPulseCheck (
                    TestSignal      => CLKR,
                    TestSignalName  => "CLKR",
                    Period          => tperiod_CLKR_NOPIPELINE_EQ_1,
                    PulseWidthHigh  => tpw_CLKR_NOPIPELINE_EQ_1_posedge,
                    PulseWidthLow   => tpw_CLKR_NOPIPELINE_EQ_1_negedge,
                    CheckEnabled    => PLFTR = '0',
                    HeaderMsg       => InstancePath & partID,
                    PeriodData      => PD_CLKR_NOPIPELINE_EQ_1,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Pviol_CLKR_NOPIPELINE_EQ_1);
                -- AL/CLKL setup/hold time check
                VitalSetupHoldCheck (
                    TestSignal      => ALIn,
                    TestSignalName  => "AL",
                    RefSignal       => CLKL,
                    RefSignalName   => "CLKL",
                    SetupHigh       => tsetup_AL0_CLKL,
                    SetupLow        => tsetup_AL0_CLKL,
                    HoldHigh        => thold_AL0_CLKL,
                    HoldLow         => thold_AL0_CLKL,
                    CheckEnabled    => TRUE,
                    RefTransition    => '/',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      =