idt70t3509m.vhd

vhdl cod for ram.For sp3e

    SIGNAL AR7_ipd        : std_logic  := 'U';
    SIGNAL AR8_ipd        : std_logic  := 'U';
    SIGNAL AR9_ipd        : std_logic  := 'U';
    SIGNAL AR10_ipd       : std_logic  := 'U';
    SIGNAL AR11_ipd       : std_logic  := 'U';
    SIGNAL AR12_ipd       : std_logic  := 'U';
    SIGNAL AR13_ipd       : std_logic  := 'U';
    SIGNAL AR14_ipd       : std_logic  := 'U';
    SIGNAL AR15_ipd       : std_logic  := 'U';
    SIGNAL AR16_ipd       : std_logic  := 'U';
    SIGNAL AR17_ipd       : std_logic  := 'U';
    SIGNAL AR18_ipd       : std_logic  := 'U';
    SIGNAL AR19_ipd       : std_logic  := 'U';
    --  Data Input/Output Bus of Left Port
    SIGNAL IOL0_ipd       : std_logic  := 'U';
    SIGNAL IOL1_ipd       : std_logic  := 'U';
    SIGNAL IOL2_ipd       : std_logic  := 'U';
    SIGNAL IOL3_ipd       : std_logic  := 'U';
    SIGNAL IOL4_ipd       : std_logic  := 'U';
    SIGNAL IOL5_ipd       : std_logic  := 'U';
    SIGNAL IOL6_ipd       : std_logic  := 'U';
    SIGNAL IOL7_ipd       : std_logic  := 'U';
    SIGNAL IOL8_ipd       : std_logic  := 'U';
    SIGNAL IOL9_ipd       : std_logic  := 'U';
    SIGNAL IOL10_ipd      : std_logic  := 'U';
    SIGNAL IOL11_ipd      : std_logic  := 'U';
    SIGNAL IOL12_ipd      : std_logic  := 'U';
    SIGNAL IOL13_ipd      : std_logic  := 'U';
    SIGNAL IOL14_ipd      : std_logic  := 'U';
    SIGNAL IOL15_ipd      : std_logic  := 'U';
    SIGNAL IOL16_ipd      : std_logic  := 'U';
    SIGNAL IOL17_ipd      : std_logic  := 'U';
    SIGNAL IOL18_ipd      : std_logic  := 'U';
    SIGNAL IOL19_ipd      : std_logic  := 'U';
    SIGNAL IOL20_ipd      : std_logic  := 'U';
    SIGNAL IOL21_ipd      : std_logic  := 'U';
    SIGNAL IOL22_ipd      : std_logic  := 'U';
    SIGNAL IOL23_ipd      : std_logic  := 'U';
    SIGNAL IOL24_ipd      : std_logic  := 'U';
    SIGNAL IOL25_ipd      : std_logic  := 'U';
    SIGNAL IOL26_ipd      : std_logic  := 'U';
    SIGNAL IOL27_ipd      : std_logic  := 'U';
    SIGNAL IOL28_ipd      : std_logic  := 'U';
    SIGNAL IOL29_ipd      : std_logic  := 'U';
    SIGNAL IOL30_ipd      : std_logic  := 'U';
    SIGNAL IOL31_ipd      : std_logic  := 'U';
    SIGNAL IOL32_ipd      : std_logic  := 'U';
    SIGNAL IOL33_ipd      : std_logic  := 'U';
    SIGNAL IOL34_ipd      : std_logic  := 'U';
    SIGNAL IOL35_ipd      : std_logic  := 'U';
--  Data Input/Output Bus of Right Port
    SIGNAL IOR0_ipd       : std_logic  := 'U';
    SIGNAL IOR1_ipd       : std_logic  := 'U';
    SIGNAL IOR2_ipd       : std_logic  := 'U';
    SIGNAL IOR3_ipd       : std_logic  := 'U';
    SIGNAL IOR4_ipd       : std_logic  := 'U';
    SIGNAL IOR5_ipd       : std_logic  := 'U';
    SIGNAL IOR6_ipd       : std_logic  := 'U';
    SIGNAL IOR7_ipd       : std_logic  := 'U';
    SIGNAL IOR8_ipd       : std_logic  := 'U';
    SIGNAL IOR9_ipd       : std_logic  := 'U';
    SIGNAL IOR10_ipd      : std_logic  := 'U';
    SIGNAL IOR11_ipd      : std_logic  := 'U';
    SIGNAL IOR12_ipd      : std_logic  := 'U';
    SIGNAL IOR13_ipd      : std_logic  := 'U';
    SIGNAL IOR14_ipd      : std_logic  := 'U';
    SIGNAL IOR15_ipd      : std_logic  := 'U';
    SIGNAL IOR16_ipd      : std_logic  := 'U';
    SIGNAL IOR17_ipd      : std_logic  := 'U';
    SIGNAL IOR18_ipd      : std_logic  := 'U';
    SIGNAL IOR19_ipd      : std_logic  := 'U';
    SIGNAL IOR20_ipd      : std_logic  := 'U';
    SIGNAL IOR21_ipd      : std_logic  := 'U';
    SIGNAL IOR22_ipd      : std_logic  := 'U';
    SIGNAL IOR23_ipd      : std_logic  := 'U';
    SIGNAL IOR24_ipd      : std_logic  := 'U';
    SIGNAL IOR25_ipd      : std_logic  := 'U';
    SIGNAL IOR26_ipd      : std_logic  := 'U';
    SIGNAL IOR27_ipd      : std_logic  := 'U';
    SIGNAL IOR28_ipd      : std_logic  := 'U';
    SIGNAL IOR29_ipd      : std_logic  := 'U';
    SIGNAL IOR30_ipd      : std_logic  := 'U';
    SIGNAL IOR31_ipd      : std_logic  := 'U';
    SIGNAL IOR32_ipd      : std_logic  := 'U';
    SIGNAL IOR33_ipd      : std_logic  := 'U';
    SIGNAL IOR34_ipd      : std_logic  := 'U';
    SIGNAL IOR35_ipd      : std_logic  := 'U';

    SIGNAL CLKL_in  : std_ulogic := '0';
    SIGNAL CLKL_out : std_ulogic := '0';
    SIGNAL CLKR_in  : std_ulogic := '0';
    SIGNAL CLKR_out : std_ulogic := '0';

BEGIN
    --------------------------------------------------------------------------
    -- Internal Delays
    --------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays
    SKEW  : VitalBuf(CLKL_out, CLKL_in, (VitalZeroDelay, tdevice_SKEW));
    SKEW1 : VitalBuf(CLKR_out, CLKR_in, (VitalZeroDelay, tdevice_SKEW));

    --------------------------------------------------------------------------
    -- Wire Delays
    --------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
        w_1   : VitalWireDelay ( CE0LNeg_ipd, CE0LNeg, tipd_CE0LNeg );
        w_2   : VitalWireDelay ( CE0RNeg_ipd, CE0RNeg, tipd_CE0RNeg );
        w_3   : VitalWireDelay ( RWL_ipd, RWL, tipd_RWL );
        w_4   : VitalWireDelay ( RWR_ipd, RWR, tipd_RWR );
        w_5   : VitalWireDelay ( OELNeg_ipd, OELNeg, tipd_OELNeg );
        w_6   : VitalWireDelay ( OERNeg_ipd, OERNeg, tipd_OERNeg );
        w_7   : VitalWireDelay ( CLKL_ipd, CLKL, tipd_CLKL );
        w_8   : VitalWireDelay ( CLKR_ipd, CLKR, tipd_CLKR );
        w_9   : VitalWireDelay ( PLFTL_ipd, PLFTL, tipd_PLFTL );
        w_10  : VitalWireDelay ( PLFTR_ipd, PLFTR, tipd_PLFTR );
        w_11  : VitalWireDelay ( ADSLNeg_ipd, ADSLNeg, tipd_ADSLNeg );
        w_12  : VitalWireDelay ( ADSRNeg_ipd, ADSRNeg, tipd_ADSRNeg );
        w_13  : VitalWireDelay ( BEL0Neg_ipd, BEL0Neg, tipd_BEL0Neg );
        w_14  : VitalWireDelay ( BEL1Neg_ipd, BEL1Neg, tipd_BEL1Neg );
        w_15  : VitalWireDelay ( BEL2Neg_ipd, BEL2Neg, tipd_BEL2Neg );
        w_16  : VitalWireDelay ( BEL3Neg_ipd, BEL3Neg, tipd_BEL3Neg );
        w_17  : VitalWireDelay ( BER0Neg_ipd, BER0Neg, tipd_BER0Neg );
        w_18  : VitalWireDelay ( BER1Neg_ipd, BER1Neg, tipd_BER1Neg );
        w_19  : VitalWireDelay ( BER2Neg_ipd, BER2Neg, tipd_BER2Neg );
        w_20  : VitalWireDelay ( BER3Neg_ipd, BER3Neg, tipd_BER3Neg );
        w_21  : VitalWireDelay ( AL0_ipd, AL0, tipd_AL0 );
        w_22  : VitalWireDelay ( AL1_ipd, AL1, tipd_AL1 );
        w_23  : VitalWireDelay ( AL2_ipd, AL2, tipd_AL3 );
        w_24  : VitalWireDelay ( AL3_ipd, AL3, tipd_AL3 );
        w_25  : VitalWireDelay ( AL4_ipd, AL4, tipd_AL4 );
        w_26  : VitalWireDelay ( AL5_ipd, AL5, tipd_AL5 );
        w_27  : VitalWireDelay ( AL6_ipd, AL6, tipd_AL6 );
        w_28  : VitalWireDelay ( AL7_ipd, AL7, tipd_AL7 );
        w_29  : VitalWireDelay ( AL8_ipd, AL8, tipd_AL8 );
        w_30  : VitalWireDelay ( AL9_ipd, AL9, tipd_AL9 );
        w_31  : VitalWireDelay ( AL10_ipd, AL10, tipd_AL10 );
        w_32  : VitalWireDelay ( AL11_ipd, AL11, tipd_AL11 );
        w_33  : VitalWireDelay ( AL12_ipd, AL12, tipd_AL12 );
        w_34  : VitalWireDelay ( AL13_ipd, AL13, tipd_AL13 );
        w_35  : VitalWireDelay ( AL14_ipd, AL14, tipd_AL14 );
        w_36  : VitalWireDelay ( AL15_ipd, AL15, tipd_AL15 );
        w_37  : VitalWireDelay ( AL16_ipd, AL16, tipd_AL16 );
        w_38  : VitalWireDelay ( AL17_ipd, AL17, tipd_AL17 );
        w_39  : VitalWireDelay ( AL18_ipd, AL18, tipd_AL18 );
        w_40  : VitalWireDelay ( AL19_ipd, AL19, tipd_AL19 );
        w_41  : VitalWireDelay ( AR0_ipd, AR0, tipd_AR0 );
        w_42  : VitalWireDelay ( AR1_ipd, AR1, tipd_AR1 );
        w_43  : VitalWireDelay ( AR2_ipd, AR2, tipd_AR2 );
        w_44  : VitalWireDelay ( AR3_ipd, AR3, tipd_AR3 );
        w_45  : VitalWireDelay ( AR4_ipd, AR4, tipd_AR4 );
        w_46  : VitalWireDelay ( AR5_ipd, AR5, tipd_AR5 );
        w_47  : VitalWireDelay ( AR6_ipd, AR6, tipd_AR6 );
        w_48  : VitalWireDelay ( AR7_ipd, AR7, tipd_AR7 );
        w_49  : VitalWireDelay ( AR8_ipd, AR8, tipd_AR8 );
        w_50  : VitalWireDelay ( AR9_ipd, AR9, tipd_AR9 );
        w_51  : VitalWireDelay ( AR10_ipd, AR10, tipd_AR10 );
        w_52  : VitalWireDelay ( AR11_ipd, AR11, tipd_AR11 );
        w_53  : VitalWireDelay ( AR12_ipd, AR12, tipd_AR12 );
        w_54  : VitalWireDelay ( AR13_ipd, AR13, tipd_AR13 );
        w_55  : VitalWireDelay ( AR14_ipd, AR14, tipd_AR14 );
        w_56  : VitalWireDelay ( AR15_ipd, AR15, tipd_AR15 );
        w_57  : VitalWireDelay ( AR16_ipd, AR16, tipd_AR16 );
        w_58  : VitalWireDelay ( AR17_ipd, AR17, tipd_AR17 );
        w_59  : VitalWireDelay ( AR18_ipd, AR18, tipd_AR18 );
        w_60  : VitalWireDelay ( AR19_ipd, AR19, tipd_AR19 );
        w_61  : VitalWireDelay ( IOL0_ipd, IOL0, tipd_IOL0 );
        w_62  : VitalWireDelay ( IOL1_ipd, IOL1, tipd_IOL1 );
        w_63  : VitalWireDelay ( IOL2_ipd, IOL2, tipd_IOL2 );
        w_64  : VitalWireDelay ( IOL3_ipd, IOL3, tipd_IOL3 );
        w_65  : VitalWireDelay ( IOL4_ipd, IOL4, tipd_IOL4 );
        w_66  : VitalWireDelay ( IOL5_ipd, IOL5, tipd_IOL5 );
        w_67  : VitalWireDelay ( IOL6_ipd, IOL6, tipd_IOL6 );
        w_68  : VitalWireDelay ( IOL7_ipd, IOL7, tipd_IOL7 );
        w_69  : VitalWireDelay ( IOL8_ipd, IOL8, tipd_IOL8 );
        w_70  : VitalWireDelay ( IOL9_ipd, IOL9, tipd_IOL9 );
        w_71  : VitalWireDelay ( IOL10_ipd, IOL10, tipd_IOL10);
        w_72  : VitalWireDelay ( IOL11_ipd, IOL11, tipd_IOL11);
        w_73  : VitalWireDelay ( IOL12_ipd, IOL12, tipd_IOL12);
        w_74  : VitalWireDelay ( IOL13_ipd, IOL13, tipd_IOL13);
        w_75  : VitalWireDelay ( IOL14_ipd, IOL14, tipd_IOL14);
        w_76  : VitalWireDelay ( IOL15_ipd, IOL15, tipd_IOL15);
        w_77  : VitalWireDelay ( IOL16_ipd, IOL16, tipd_IOL16);
        w_78  : VitalWireDelay ( IOL17_ipd, IOL17, tipd_IOL17);
        w_79  : VitalWireDelay ( IOL18_ipd, IOL18, tipd_IOL18);
        w_80  : VitalWireDelay ( IOL19_ipd, IOL19, tipd_IOL19);
        w_81  : VitalWireDelay ( IOL20_ipd, IOL20, tipd_IOL20);
        w_82  : VitalWireDelay ( IOL21_ipd, IOL21, tipd_IOL21);
        w_83  : VitalWireDelay ( IOL22_ipd, IOL22, tipd_IOL22);
        w_84  : VitalWireDelay ( IOL23_ipd, IOL23, tipd_IOL23);
        w_85  : VitalWireDelay ( IOL24_ipd, IOL24, tipd_IOL24);
        w_86  : VitalWireDelay ( IOL25_ipd, IOL25, tipd_IOL25);
        w_87  : VitalWireDelay ( IOL26_ipd, IOL26, tipd_IOL26);
        w_88  : VitalWireDelay ( IOL27_ipd, IOL27, tipd_IOL27);
        w_89  : VitalWireDelay ( IOL28_ipd, IOL28, tipd_IOL28);
        w_90  : VitalWireDelay ( IOL29_ipd, IOL29, tipd_IOL29);
        w_91  : VitalWireDelay ( IOL30_ipd, IOL30, tipd_IOL30);
        w_92  : VitalWireDelay ( IOL31_ipd, IOL31, tipd_IOL31);
        w_93  : VitalWireDelay ( IOL32_ipd, IOL32, tipd_IOL32);
        w_94  : VitalWireDelay ( IOL33_ipd, IOL33, tipd_IOL33);
        w_95  : VitalWireDelay ( IOL34_ipd, IOL34, tipd_IOL34);
        w_96  : VitalWireDelay ( IOL35_ipd, IOL35, tipd_IOL35);
        w_97  : VitalWireDelay ( IOR0_ipd, IOR0, tipd_IOR0 );
        w_98  : VitalWireDelay ( IOR1_ipd, IOR1, tipd_IOR1 );
        w_99  : VitalWireDelay ( IOR2_ipd, IOR2, tipd_IOR2 );
        w_100 : VitalWireDelay ( IOR3_ipd, IOR3, tipd_IOR3 );
        w_101 : VitalWireDelay ( IOR4_ipd, IOR4, tipd_IOR4 );
        w_102 : VitalWireDelay ( IOR5_ipd, IOR5, tipd_IOR5 );
        w_103 : VitalWireDelay ( IOR6_ipd, IOR6, tipd_IOR6 );
        w_104 : VitalWireDelay ( IOR7_ipd, IOR7, tipd_IOR7 );
        w_105 : VitalWireDelay ( IOR8_ipd, IOR8, tipd_IOR8 );
        w_106 : VitalWireDelay ( IOR9_ipd, IOR9, tipd_IOR9 );
        w_107 : VitalWireDelay ( IOR10_ipd, IOR10, tipd_IOR10);
        w_108 : VitalWireDelay ( IOR11_ipd, IOR11, tipd_IOR11);
        w_109 : VitalWireDelay ( IOR12_ipd, IOR12, tipd_IOR12);
        w_110 : VitalWireDelay ( IOR13_ipd, IOR13, tipd_IOR13);
        w_111 : VitalWireDelay ( IOR14_ipd, IOR14, tipd_IOR14);
        w_112 : VitalWireDelay ( IOR15_ipd, IOR15, tipd_IOR15);
        w_113 : VitalWireDelay ( IOR16_ipd, IOR16, tipd_IOR16);
        w_114 : VitalWireDelay ( IOR17_ipd, IOR17, tipd_IOR17);
        w_115 : VitalWireDelay ( IOR18_ipd, IOR18, tipd_IOR18);
        w_116 : VitalWireDelay ( IOR19_ipd, IOR19, tipd_IOR19);
        w_117 : VitalWireDelay ( IOR20_ipd, IOR20, tipd_IOR20);
        w_118 : VitalWireDelay ( IOR21_ipd, IOR21, tipd_IOR21);
        w_119 : VitalWireDelay ( IOR22_ipd, IOR22, tipd_IOR22);
        w_120 : VitalWireDelay ( IOR23_ipd, IOR23, tipd_IOR23);
        w_121 : VitalWireDelay ( IOR24_ipd, IOR24, tipd_IOR24);
        w_122 : VitalWireDelay ( IOR25_ipd, IOR25, tipd_IOR25);
        w_123 : VitalWireDelay ( IOR26_ipd, IOR26, tipd_IOR26);
        w_124 : VitalWireDelay ( IOR27_ipd, IOR27, tipd_IOR27);
        w_125 : VitalWireDelay ( IOR28_ipd, IOR28, tipd_IOR28);
        w_126 : VitalWireDelay ( IOR29_ipd, IOR29, tipd_IOR29);
        w_127 : VitalWireDelay ( IOR30_ipd, IOR30, tipd_IOR30);
        w_128 : VitalWireDelay ( IOR31_ipd, IOR31, tipd_IOR31);
        w_129 : VitalWireDelay ( IOR32_ipd, IOR32, tipd_IOR32);
        w_130 : VitalWireDelay ( IOR33_ipd, IOR33, tipd_IOR33);
        w_131 : VitalWireDelay ( IOR34_ipd, IOR34, tipd_IOR34);
        w_132 : VitalWireDelay ( IOR35_ipd, IOR35, tipd_IOR35);
        w_133 : VitalWireDelay ( CNTENLNeg_ipd, CNTENLNeg, tipd_CNTENLNeg );
        w_134 : VitalWireDelay ( CNTENRNeg_ipd, CNTENRNeg, tipd_CNTENRNeg );
        w_135 : VitalWireDelay ( CE1L_ipd, CE1L, tipd_CE1L );
        w_136 : VitalWireDelay ( CE1R_ipd, CE1R, tipd_CE1R );
        w_137 : VitalWireDelay ( REPEATLNeg_ipd, REPEATLNeg, tipd_REPEATLNeg );
        w_138 : VitalWireDelay ( REPEATRNeg_ipd, REPEATRNeg, tipd_REPEATRNeg );
        w_139 : VitalWireDelay ( ZZL_ipd, ZZL, tipd_ZZL);
        w_140 : VitalWireDelay ( ZZR_ipd, ZZR, tipd_ZZR);
    END BLOCK WireDelay;

    ---------------------------------------------------------------------------
    -- Main Behavior Block
    ---------------------------------------------------------------------------
    Behavior : BLOCK