idt70t3509m.vhd

vhdl cod for ram.For sp3e

        UserPreload    : BOOLEAN := FALSE;
        -- For FMF SDF technology file usage
        TimingModel    : STRING  := DefaultTimingModel
        );

    PORT (
        --Chip Enables 0
        CE0LNeg    : IN    std_ulogic := 'U';
        CE0RNeg    : IN    std_ulogic := 'U';
        --Chip Enables 1
        CE1L       : IN    std_ulogic := 'U';
        CE1R       : IN    std_ulogic := 'U';
        --Read/Write Enable
        RWL        : IN    std_ulogic := 'U';
        RWR        : IN    std_ulogic := 'U';
        -- Output Enable
        OELNeg     : IN    std_ulogic := 'U';
        OERNeg     : IN    std_ulogic := 'U';
        -- Clk
        CLKL       : IN    std_logic  := 'U';
        CLKR       : IN    std_logic  := 'U';
        --Pipeline/Flow-Through
        PLFTL      : IN    std_logic  := 'U';
        PLFTR      : IN    std_logic  := 'U';
        --Adress Strobe Enable
        ADSLNeg    : IN    std_logic  := 'U';
        ADSRNeg    : IN    std_logic  := 'U';
        --Counter Enable
        CNTENLNeg  : IN    std_logic  := 'U';
        CNTENRNeg  : IN    std_logic  := 'U';
        -- Counter Repeat
        REPEATLNeg : IN    std_logic  := 'U';
        REPEATRNeg : IN    std_logic  := 'U';
        --Left Byte Enables
        BEL0Neg    : IN    std_logic  := 'U';
        BEL1Neg    : IN    std_logic  := 'U';
        BEL2Neg    : IN    std_logic  := 'U';
        BEL3Neg    : IN    std_logic  := 'U';
        --Right Byte Enables
        BER0Neg    : IN    std_logic  := 'U';
        BER1Neg    : IN    std_logic  := 'U';
        BER2Neg    : IN    std_logic  := 'U';
        BER3Neg    : IN    std_logic  := 'U';
        -- Sleep mode pin
        ZZL        : IN    std_ulogic := 'U';
        ZZR        : IN    std_ulogic := 'U';
        --Left Adress
        AL0        : IN    std_logic  := 'U';
        AL1        : IN    std_logic  := 'U';
        AL2        : IN    std_logic  := 'U';
        AL3        : IN    std_logic  := 'U';
        AL4        : IN    std_logic  := 'U';
        AL5        : IN    std_logic  := 'U';
        AL6        : IN    std_logic  := 'U';
        AL7        : IN    std_logic  := 'U';
        AL8        : IN    std_logic  := 'U';

        AL9        : IN    std_logic  := 'U';
        AL10       : IN    std_logic  := 'U';
        AL11       : IN    std_logic  := 'U';
        AL12       : IN    std_logic  := 'U';
        AL13       : IN    std_logic  := 'U';
        AL14       : IN    std_logic  := 'U';
        AL15       : IN    std_logic  := 'U';
        AL16       : IN    std_logic  := 'U';
        AL17       : IN    std_logic  := 'U';
        AL18       : IN    std_logic  := 'U';
        AL19       : IN    std_logic  := 'U';
        -- Right Adress
        AR0        : IN    std_logic  := 'U';
        AR1        : IN    std_logic  := 'U';
        AR2        : IN    std_logic  := 'U';
        AR3        : IN    std_logic  := 'U';
        AR4        : IN    std_logic  := 'U';
        AR5        : IN    std_logic  := 'U';
        AR6        : IN    std_logic  := 'U';
        AR7        : IN    std_logic  := 'U';
        AR8        : IN    std_logic  := 'U';
        AR9        : IN    std_logic  := 'U';
        AR10       : IN    std_logic  := 'U';
        AR11       : IN    std_logic  := 'U';
        AR12       : IN    std_logic  := 'U';
        AR13       : IN    std_logic  := 'U';
        AR14       : IN    std_logic  := 'U';
        AR15       : IN    std_logic  := 'U';
        AR16       : IN    std_logic  := 'U';
        AR17       : IN    std_logic  := 'U';
        AR18       : IN    std_logic  := 'U';
        AR19       : IN    std_logic  := 'U';
        --  Data Input/Output Bus of Left Port
        IOL0       : INOUT std_logic  := 'U';
        IOL1       : INOUT std_logic  := 'U';
        IOL2       : INOUT std_logic  := 'U';
        IOL3       : INOUT std_logic  := 'U';
        IOL4       : INOUT std_logic  := 'U';
        IOL5       : INOUT std_logic  := 'U';
        IOL6       : INOUT std_logic  := 'U';
        IOL7       : INOUT std_logic  := 'U';
        IOL8       : INOUT std_logic  := 'U';
        IOL9       : INOUT std_logic  := 'U';
        IOL10      : INOUT std_logic  := 'U';
        IOL11      : INOUT std_logic  := 'U';
        IOL12      : INOUT std_logic  := 'U';
        IOL13      : INOUT std_logic  := 'U';
        IOL14      : INOUT std_logic  := 'U';
        IOL15      : INOUT std_logic  := 'U';
        IOL16      : INOUT std_logic  := 'U';
        IOL17      : INOUT std_logic  := 'U';
        IOL18      : INOUT std_logic  := 'U';
        IOL19      : INOUT std_logic  := 'U';
        IOL20      : INOUT std_logic  := 'U';
        IOL21      : INOUT std_logic  := 'U';
        IOL22      : INOUT std_logic  := 'U';
        IOL23      : INOUT std_logic  := 'U';
        IOL24      : INOUT std_logic  := 'U';
        IOL25      : INOUT std_logic  := 'U';
        IOL26      : INOUT std_logic  := 'U';
        IOL27      : INOUT std_logic  := 'U';
        IOL28      : INOUT std_logic  := 'U';
        IOL29      : INOUT std_logic  := 'U';
        IOL30      : INOUT std_logic  := 'U';
        IOL31      : INOUT std_logic  := 'U';
        IOL32      : INOUT std_logic  := 'U';
        IOL33      : INOUT std_logic  := 'U';
        IOL34      : INOUT std_logic  := 'U';
        IOL35      : INOUT std_logic  := 'U';
        --  Data Input/Output Bus of Right Port
        IOR0       : INOUT std_logic  := 'U';
        IOR1       : INOUT std_logic  := 'U';
        IOR2       : INOUT std_logic  := 'U';
        IOR3       : INOUT std_logic  := 'U';
        IOR4       : INOUT std_logic  := 'U';
        IOR5       : INOUT std_logic  := 'U';
        IOR6       : INOUT std_logic  := 'U';
        IOR7       : INOUT std_logic  := 'U';
        IOR8       : INOUT std_logic  := 'U';
        IOR9       : INOUT std_logic  := 'U';
        IOR10      : INOUT std_logic  := 'U';
        IOR11      : INOUT std_logic  := 'U';
        IOR12      : INOUT std_logic  := 'U';
        IOR13      : INOUT std_logic  := 'U';
        IOR14      : INOUT std_logic  := 'U';
        IOR15      : INOUT std_logic  := 'U';
        IOR16      : INOUT std_logic  := 'U';
        IOR17      : INOUT std_logic  := 'U';
        IOR18      : INOUT std_logic  := 'U';
        IOR19      : INOUT std_logic  := 'U';
        IOR20      : INOUT std_logic  := 'U';
        IOR21      : INOUT std_logic  := 'U';
        IOR22      : INOUT std_logic  := 'U';
        IOR23      : INOUT std_logic  := 'U';
        IOR24      : INOUT std_logic  := 'U';
        IOR25      : INOUT std_logic  := 'U';
        IOR26      : INOUT std_logic  := 'U';
        IOR27      : INOUT std_logic  := 'U';
        IOR28      : INOUT std_logic  := 'U';
        IOR29      : INOUT std_logic  := 'U';
        IOR30      : INOUT std_logic  := 'U';
        IOR31      : INOUT std_logic  := 'U';
        IOR32      : INOUT std_logic  := 'U';
        IOR33      : INOUT std_logic  := 'U';
        IOR34      : INOUT std_logic  := 'U';
        IOR35      : INOUT std_logic  := 'U';
        -- Interrup Flag
        INTLNeg    : OUT   std_ulogic := 'U';
        INTRNeg    : OUT   std_ulogic := 'U'
        );

    ATTRIBUTE vital_level0 OF idt70T3509m : ENTITY IS True;
END idt70t3509m;
-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------

ARCHITECTURE vhdl_behavioral of idt70T3509m IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT MaxData : NATURAL := 16#1FF#;
    CONSTANT MemSize : NATURAL := 1048575;
    CONSTANT HiAbit  : NATURAL := 19;
    CONSTANT HiDbit  : NATURAL := 35;
    CONSTANT FF_ADDR : NATURAL := 16#FFFFF#;
    CONSTANT FE_ADDR : NATURAL := 16#FFFFe#;
    CONSTANT partID  : STRING  := "idt70t3509m";

    SIGNAL CE0LNeg_ipd    : std_ulogic := 'U';
    SIGNAL CE0RNeg_ipd    : std_ulogic := 'U';
    SIGNAL CE1L_ipd       : std_ulogic := 'U';
    SIGNAL CE1R_ipd       : std_ulogic := 'U';
    --Read/Write Enable
    SIGNAL RWL_ipd        : std_ulogic := 'U';
    SIGNAL RWR_ipd        : std_ulogic := 'U';
    -- Output Enable
    SIGNAL OELNeg_ipd     : std_ulogic := 'U';
    SIGNAL OERNeg_ipd     : std_ulogic := 'U';
    -- Clk
    SIGNAL CLKL_ipd       : std_logic  := 'U';
    SIGNAL CLKR_ipd       : std_logic  := 'U';
    --Pipeline/Flow-Through
    SIGNAL PLFTL_ipd      : std_logic  := 'U';
    SIGNAL PLFTR_ipd      : std_logic  := 'U';
    --Adress Strobe Enable
    SIGNAL ADSLNeg_ipd    : std_logic  := 'U';
    SIGNAL ADSRNeg_ipd    : std_logic  := 'U';
    --Counter Enable
    SIGNAL CNTENLNeg_ipd  : std_logic  := 'U';
    SIGNAL CNTENRNeg_ipd  : std_logic  := 'U';
    --Counter REPEAT
    SIGNAL REPEATLNeg_ipd : std_logic  := 'U';
    SIGNAL REPEATRNeg_ipd : std_logic  := 'U';
    --Left Byte Enables
    SIGNAL BEL0Neg_ipd    : std_logic  := 'U';
    SIGNAL BEL1Neg_ipd    : std_logic  := 'U';
    SIGNAL BEL2Neg_ipd    : std_logic  := 'U';
    SIGNAL BEL3Neg_ipd    : std_logic  := 'U';
    --Right Byte Enables
    SIGNAL BER0Neg_ipd    : std_logic  := 'U';
    SIGNAL BER1Neg_ipd    : std_logic  := 'U';
    SIGNAL BER2Neg_ipd    : std_logic  := 'U';
    SIGNAL BER3Neg_ipd    : std_logic  := 'U';
    -- Sleep bit
    SIGNAL ZZL_ipd        : std_logic  := 'U';
    SIGNAL ZZR_ipd        : std_logic  := 'U';
    --Left Adress
    SIGNAL AL0_ipd        : std_logic  := 'U';
    SIGNAL AL1_ipd        : std_logic  := 'U';
    SIGNAL AL2_ipd        : std_logic  := 'U';
    SIGNAL AL3_ipd        : std_logic  := 'U';
    SIGNAL AL4_ipd        : std_logic  := 'U';
    SIGNAL AL5_ipd        : std_logic  := 'U';
    SIGNAL AL6_ipd        : std_logic  := 'U';
    SIGNAL AL7_ipd        : std_logic  := 'U';
    SIGNAL AL8_ipd        : std_logic  := 'U';
    SIGNAL AL9_ipd        : std_logic  := 'U';
    SIGNAL AL10_ipd       : std_logic  := 'U';
    SIGNAL AL11_ipd       : std_logic  := 'U';
    SIGNAL AL12_ipd       : std_logic  := 'U';
    SIGNAL AL13_ipd       : std_logic  := 'U';
    SIGNAL AL14_ipd       : std_logic  := 'U';
    SIGNAL AL15_ipd       : std_logic  := 'U';
    SIGNAL AL16_ipd       : std_logic  := 'U';
    SIGNAL AL17_ipd       : std_logic  := 'U';
    SIGNAL AL18_ipd       : std_logic  := 'U';
    SIGNAL AL19_ipd       : std_logic  := 'U';
    -- Right Adress
    SIGNAL AR0_ipd        : std_logic  := 'U';
    SIGNAL AR1_ipd        : std_logic  := 'U';
    SIGNAL AR2_ipd        : std_logic  := 'U';
    SIGNAL AR3_ipd        : std_logic  := 'U';
    SIGNAL AR4_ipd        : std_logic  := 'U';
    SIGNAL AR5_ipd        : std_logic  := 'U';
    SIGNAL AR6_ipd        : std_logic  := 'U';