cy7c1363.vhd

vhdl cod for ram.For sp3e

                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);

                    WHEN read_burst =>
                        state <= read;
                        Burst_Cnt := Burst_Cnt + 1;
                        offset := Burst_Seq(memstart)(Burst_Cnt);
                        MemAddr := startaddr + offset;
                        ReadMem(MemAddr);

                    WHEN read_susp =>
                        null;
                END CASE;

            WHEN SPwrite =>
                CASE command IS
                    WHEN ds =>
                        state <= desel;
                        OBuf1 := (others => 'Z');

                    WHEN begin_rw =>
                        state <= begin_rdwr;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        ReadMem(MemAddr);

                    WHEN SCwr =>
                        state <= SCwrite;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);

                    WHEN SPwr_burst =>
                        Burst_Cnt := Burst_Cnt + 1;
                        IF (Burst_Cnt = 4) THEN
                            Burst_Cnt := 0;
                        END IF;
                        offset := Burst_Seq(memstart)(Burst_Cnt);
                        MemAddr := startaddr + offset;
                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);

                    WHEN SPwr_susp =>
                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);

                    WHEN others =>
                        null;

                END CASE;

            WHEN SCwrite =>
                Burst_Cnt := 0;
                CASE command IS
                    WHEN ds =>
                        state <= desel;

                    WHEN begin_rw =>
                        state <= begin_rdwr;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        ReadMem(MemAddr);

                    WHEN SCwr =>
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);

                    WHEN SPwr_burst =>
                        state <= SPwrite;
                        Burst_Cnt := Burst_Cnt + 1;
                        offset := Burst_Seq(memstart)(Burst_Cnt);
                        MemAddr := startaddr + offset;
                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);

                    WHEN others =>
                        null;

                END CASE;

            WHEN read =>
                CASE command IS
                    WHEN ds =>
                        state <= desel;
                        OBuf1 := (others => 'Z');

                    WHEN begin_rw =>
                        state <= begin_rdwr;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        ReadMem(MemAddr);

                    WHEN SCwr =>
                        state <= SCwrite;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        OBuf1 := (others => 'Z');
                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);

                    WHEN SPwr_burst =>
                        OBuf1 := (others => 'Z');

                    WHEN SPwr_susp =>
                        OBuf1 := (others => 'Z');

                    WHEN read_burst =>
                        state <= read;
                        Burst_Cnt := Burst_Cnt + 1;
                        IF (Burst_Cnt = 4) THEN
                            Burst_Cnt := 0;
                        END IF;
                        offset := Burst_Seq(memstart)(Burst_Cnt);
                        MemAddr := startaddr + offset;
                        ReadMem(MemAddr);

                    WHEN read_susp =>
                        state <= read;
                END CASE;
        END CASE;

        IF (OENegIn = '0') THEN
            IF OBuf1(0) /= 'Z' AND command /= read_susp THEN
                D_zd <= (others => 'X'), OBuf1 AFTER 1 ns;
            ELSE
                D_zd <= OBuf1;
            END IF;
        END IF;

    END IF;

    IF (OENegIn = '1') THEN
        D_zd <= (others => 'Z');
    ELSIF falling_edge(OENegIn) AND (ZZIn = '0') AND zz_reset THEN
        IF OBuf1(0) /= 'Z' THEN
            D_zd <= (others => 'X'), OBuf1 AFTER 1 ns;
        ELSE
            D_zd <= OBuf1;
        END IF;
    END IF;

    IF rising_edge(ZZIn) THEN
        IF state/= desel THEN
            ASSERT false
                REPORT InstancePath & partID & ": Device must be "
                &  "deselected prior to entering the sleep mode."
                SEVERITY SeverityMode;
        END IF;
        zz_set := TRUE;
        IF NOT(zz_reset) THEN
            zz_set := FALSE;
            zz_reset := TRUE;
            zz_cnt := 0;
            ASSERT false
                REPORT InstancePath & partID & ": 2tCYC are "
                       &  "required to exit from sleep mode."
                SEVERITY SeverityMode;
        END IF;
    ELSIF falling_edge(ZZIn) THEN
        zz_reset := FALSE;
        IF zz_set THEN
            zz_set := FALSE;
            zz_reset := TRUE;
            zz_cnt := 0;
            ASSERT false
                REPORT InstancePath & partID & ": 2tCYC are "
                       & "required to enter into sleep mode."
                SEVERITY SeverityMode;
        END IF;
    END IF;

    IF rising_edge(CLKIn) THEN
        IF zz_set THEN
            D_zd <= (others => 'Z');
            IF zz_cnt = 2 THEN
                zz_set := FALSE;
                zz_cnt := 0;
            ELSE
                zz_cnt := zz_cnt + 1;
            END IF;
        ELSIF NOT(zz_reset) THEN
            IF zz_cnt = 2 THEN
                zz_reset := TRUE;
                zz_cnt := 0;
            ELSE
                zz_cnt := zz_cnt + 1;
            END IF;
        END IF;
    END IF;

    IF NOT(zz_reset) THEN
        IF (ADSPNIn = '0' OR ADSCNIn = '0' OR
            CENeg = '0' OR CE2 = '1' OR CE2Neg = '0') THEN
            ASSERT FALSE
                REPORT InstancePath & partID & ": ADSC, ADSP and Chip Enable "&
                "inputs must not be asserted for at least 2tCYC after leaving"&
                " ZZ state"
            SEVERITY SeverityMode;
        END IF;
    END IF;

    END PROCESS;

    ------------------------------------------------------------------------
    -- Path Delay Process
    ------------------------------------------------------------------------
    DataOutPath : FOR I IN 17 DOWNTO 0 GENERATE
        DataOut_Delay : PROCESS (D_zd(i))
            VARIABLE D_GlitchData:VitalGlitchDataArrayType(17 Downto 0);
        BEGIN
            VitalPathDelay01Z (
                OutSignal       => DataOut(i),
                OutSignalName   => "Data",
                OutTemp         => D_zd(i),
                Mode            => VitalTransport,
                GlitchData      => D_GlitchData(i),
                Paths           => (
                0 => (InputChangeTime => CLKIn'LAST_EVENT,
                      PathDelay => tpd_CLK_DQA0,
                      PathCondition   => OENegIn = '0' AND CLKIn = '1'
                                         AND D_zd(i) /= 'X'),
                1 => (InputChangeTime => CLKIn'LAST_EVENT,
                      PathDelay => tpd_CLK_DQA1,
                      PathCondition   => OENegIn = '0' AND CLKIn = '1'
                                         AND D_zd(i) = 'X'),
                2 => (InputChangeTime => OENegIn'LAST_EVENT,
                      PathDelay => tpd_OENeg_DQA0,
                      PathCondition   => D_zd(i) /= 'X'),
                3 => (InputChangeTime => OENegIn'LAST_EVENT,
                      PathDelay => tpd_OENeg_DQA1,
                      PathCondition   => D_zd(i) = 'X')
                )
            );
        END PROCESS;
    END GENERATE;

    --------------------------------------------------------------------------
    -- File Read Section
    --------------------------------------------------------------------------
    --  cy7c1363 memory file
    --  /         - comment
    --  @aaaaa    - <aaaaa> stands for address
    --  ddddd     - <ddddd> is a 18-bit data, MemDataA(aaaaa++) is loaded with
    --              nine LSBs and MemDataB(aaaaa++) is loaded with nine MSBs
    --             (aaaaa is incremented at every load)
    --  only first 1-6 columns are loaded. NO empty lines !!!!!!!!!!!!!!!!!!!
    --------------------------------------------------------------------------
    default: PROCESS IS

        VARIABLE ind        : NATURAL := 0;
        VARIABLE linecnt    : NATURAL := 0;
        VARIABLE buf        : line;

    BEGIN
        IF (mem_file_name /= "none") AND (NOW < 1 ns) THEN
            ind := 0;
            linecnt := 0;
            WHILE (not ENDFILE (mem_file)) LOOP
                READLINE (mem_file, buf);
                linecnt := linecnt +1;
                IF buf(1) = '/' THEN     --comment
                    NEXT;
                ELSIF buf(1) = '@' THEN  --address
                    ind := h(buf(2 to 6));
                ELSE
                    IF ind <= MemSize THEN
                        MemDataA(ind) := (h(buf(3 to 5)) MOD 512);
                        MemDataB(ind) := ((h(buf(1 to 3))/2) MOD 512);
                        ind := ind + 1;
                    ELSE
                        ASSERT FALSE
                        REPORT "file: "&mem_file_name&" has size larger than "
                        &to_int_str(MemSize+1)&" at line "&to_int_str(linecnt)
                        SEVERITY warning;
                    END IF;
                END IF;
            END LOOP;
        END IF;
        WAIT;
    END PROCESS default;

    END BLOCK;

END vhdl_behavioral;