cy7c1363.vhd

vhdl cod for ram.For sp3e

        );
        PORT MAP (
            BWANIn        =>  BWANeg_ipd,
            BWBNIn        =>  BWBNeg_ipd,
            GWNIn         =>  GWNeg_ipd,
            BWENIn        =>  BWENeg_ipd,
            CLKIn         =>  CLK_ipd,
            OENegIn       =>  OENeg_ipd,
            ADVNIn        =>  ADVNeg_ipd,
            ADSPNIn       =>  ADSPNeg_ipd,
            ADSCNIn       =>  ADSCNeg_ipd,
            MODEIn        =>  MODE_ipd,
            ZZIn          =>  ZZ_ipd,
            CE2In         =>  CE2_ipd,
            CENegIn       =>  CENeg_ipd,
            CE2NegIn      =>  CE2Neg_ipd,
            DataOut(0)    =>  DQA0,
            DataOut(1)    =>  DQA1,
            DataOut(2)    =>  DQA2,
            DataOut(3)    =>  DQA3,
            DataOut(4)    =>  DQA4,
            DataOut(5)    =>  DQA5,
            DataOut(6)    =>  DQA6,
            DataOut(7)    =>  DQA7,
            DataOut(8)    =>  DQA8,
            DataOut(9)    =>  DQB0,
            DataOut(10)   =>  DQB1,
            DataOut(11)   =>  DQB2,
            DataOut(12)   =>  DQB3,
            DataOut(13)   =>  DQB4,
            DataOut(14)   =>  DQB5,
            DataOut(15)   =>  DQB6,
            DataOut(16)   =>  DQB7,
            DataOut(17)   =>  DQB8,
            DatAIn(0)     =>  DQA0_ipd,
            DatAIn(1)     =>  DQA1_ipd,
            DatAIn(2)     =>  DQA2_ipd,
            DatAIn(3)     =>  DQA3_ipd,
            DatAIn(4)     =>  DQA4_ipd,
            DatAIn(5)     =>  DQA5_ipd,
            DatAIn(6)     =>  DQA6_ipd,
            DatAIn(7)     =>  DQA7_ipd,
            DatAIn(8)     =>  DQA8_ipd,
            DatBIn(0)     =>  DQB0_ipd,
            DatBIn(1)     =>  DQB1_ipd,
            DatBIn(2)     =>  DQB2_ipd,
            DatBIn(3)     =>  DQB3_ipd,
            DatBIn(4)     =>  DQB4_ipd,
            DatBIn(5)     =>  DQB5_ipd,
            DatBIn(6)     =>  DQB6_ipd,
            DatBIn(7)     =>  DQB7_ipd,
            DatBIn(8)     =>  DQB8_ipd,
            AddressIn(0)  =>  A0_ipd,
            AddressIn(1)  =>  A1_ipd,
            AddressIn(2)  =>  A2_ipd,
            AddressIn(3)  =>  A3_ipd,
            AddressIn(4)  =>  A4_ipd,
            AddressIn(5)  =>  A5_ipd,
            AddressIn(6)  =>  A6_ipd,
            AddressIn(7)  =>  A7_ipd,
            AddressIn(8)  =>  A8_ipd,
            AddressIn(9)  =>  A9_ipd,
            AddressIn(10) =>  A10_ipd,
            AddressIn(11) =>  A11_ipd,
            AddressIn(12) =>  A12_ipd,
            AddressIn(13) =>  A13_ipd,
            AddressIn(14) =>  A14_ipd,
            AddressIn(15) =>  A15_ipd,
            AddressIn(16) =>  A16_ipd,
            AddressIn(17) =>  A17_ipd,
            AddressIn(18) =>  A18_ipd
        );
        -- Type definition for state machine
        TYPE mem_state IS (desel,
                           begin_rdwr,
                           SPwrite,
                           SCwrite,
                           read
                          );

        SIGNAL state     : mem_state;

        TYPE sequence IS ARRAY (0 to 3) OF INTEGER RANGE -3 to 3;
        TYPE seqtab IS ARRAY (0 to 3) OF sequence;

        FILE mem_file    : text IS mem_file_name;

        CONSTANT il0 : sequence := (0, 1, 2, 3);
        CONSTANT il1 : sequence := (0, -1, 2, 1);
        CONSTANT il2 : sequence := (0, 1, -2, -1);
        CONSTANT il3 : sequence := (0, -1, -2, -3);
        CONSTANT il  : seqtab := (il0, il1, il2, il3);

        CONSTANT ln0 : sequence := (0, 1, 2, 3);
        CONSTANT ln1 : sequence := (0, 1, 2, -1);
        CONSTANT ln2 : sequence := (0, 1, -2, -1);
        CONSTANT ln3 : sequence := (0, -3, -2, -1);
        CONSTANT ln  : seqtab := (ln0, ln1, ln2, ln3);

        CONSTANT MemSize : INTEGER := 16#7FFFF#;  -- 512K
        CONSTANT MaxData : INTEGER := 16#1FF#;    -- 511

        -- Memory array declaration
        TYPE MemStore IS ARRAY (0 to MemSize) OF INTEGER
                         RANGE  -2 TO MaxData;

        SHARED VARIABLE MemDataA   : MemStore;
        SHARED VARIABLE MemDataB   : MemStore;

        -- Functionality Results Variables
        SHARED VARIABLE Violation  : X01 := '0';

        SHARED VARIABLE OBuf1      : std_logic_vector(17 DOWNTO 0)
                                   := (OTHERS => 'Z');

        SIGNAL Burst_Seq : seqtab := ln;
        SIGNAL D_zd      : std_logic_vector(17 DOWNTO 0);

        PROCEDURE ReadMem
            (RAddr     : IN natural)
        IS
        BEGIN
            IF MemDataA(RAddr) = -2 THEN
                OBuf1(8 downto 0) := (others => 'U');
            ELSIF MemDataA(RAddr) = -1 THEN
                OBuf1(8 downto 0) := (others => 'X');
            ELSE
                OBuf1(8 downto 0) := to_slv(MemDataA(RAddr),9);
            END IF;
            IF MemDataB(RAddr) = -2 THEN
                OBuf1(17 downto 9) := (others => 'U');
            ELSIF MemDataB(RAddr) = -1 THEN
                OBuf1(17 downto 9) := (others => 'X');
            ELSE
                OBuf1(17 downto 9) := to_slv(MemDataB(RAddr),9);
            END IF;
        END PROCEDURE ReadMem;

        PROCEDURE WriteMem
            (WAddr     : IN natural;
             WDatA     : IN std_logic_vector(8 downto 0);
             WDatB     : IN std_logic_vector(8 downto 0);
             WGWN      : IN std_logic;
             WBWA      : IN std_logic;
             WBWB      : IN std_logic)
        IS
        BEGIN
            IF WGWN = '0' THEN
                MemDataA(WAddr) := -1;
                MemDataB(WAddr) := -1;
                IF Violation /= 'X' THEN
                    MemDataA(WAddr) := to_nat(WDatA);
                    MemDataB(WAddr) := to_nat(WDatB);
                END IF;
            ELSE
                IF (WBWA = '0') THEN
                    MemDataA(WAddr) := -1;
                    IF Violation /= 'X' THEN
                        MemDataA(WAddr) := to_nat(WDatA);
                    END IF;
                END IF;
                IF (WBWB = '0') THEN
                    MemDataB(WAddr) := -1;
                    IF Violation /= 'X' THEN
                        MemDataB(WAddr) := to_nat(WDatB);
                    END IF;
                END IF;
            END IF;
        END PROCEDURE WriteMem;

    BEGIN

        Burst_Setup : PROCESS (MODEIn)

        BEGIN

           IF (MODEIn = '0') THEN
               Burst_Seq <= ln;  -- linear burst
           ELSE
               Burst_Seq <= il;  -- interleaved burst
           END IF;

        END PROCESS Burst_Setup;

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
        Behavior : PROCESS (BWANIn, BWBNIn, DatAIn, DatBIn, CLKIn, AddressIn,
                            GWNIn, BWENIn, OENegIn, ADVNIn, ADSPNIn, ADSCNIn,
                            CE2In, CENegIn, CE2NegIn, ZZIn)

            -- Type definition for commands
            TYPE command_type is (ds,
                                  SPwr_burst,
                                  SPwr_susp,
                                  SCwr,
                                  begin_rw,
                                  read_burst,
                                  read_susp
                                 );

            -- Timing Check Variables

            VARIABLE Tviol_AddressIn_CLK : X01 := '0';
            VARIABLE TD_AddressIn_CLK    : VitalTimingDataType;

            VARIABLE Tviol_DatBIn_CLK    : X01 := '0';
            VARIABLE TD_DatBIn_CLK       : VitalTimingDataType;

            VARIABLE Tviol_DatAIn_CLK    : X01 := '0';
            VARIABLE TD_DatAIn_CLK       : VitalTimingDataType;

            VARIABLE Tviol_BWBN_CLK      : X01 := '0';
            VARIABLE TD_BWBN_CLK         : VitalTimingDataType;

            VARIABLE Tviol_BWAN_CLK      : X01 := '0';
            VARIABLE TD_BWAN_CLK         : VitalTimingDataType;

            VARIABLE Tviol_BWEN_CLK      : X01 := '0';
            VARIABLE TD_BWEN_CLK         : VitalTimingDataType;

            VARIABLE Tviol_GWN_CLK       : X01 := '0';
            VARIABLE TD_GWN_CLK          : VitalTimingDataType;

            VARIABLE Tviol_ADVNIn_CLK    : X01 := '0';
            VARIABLE TD_ADVNIn_CLK       : VitalTimingDataType;

            VARIABLE Tviol_ADSCNIn_CLK   : X01 := '0';
            VARIABLE TD_ADSCNIn_CLK      : VitalTimingDataType;

            VARIABLE Tviol_ADSPNIn_CLK   : X01 := '0';
            VARIABLE TD_ADSPNIn_CLK      : VitalTimingDataType;

            VARIABLE Tviol_CENegIn_CLK   : X01 := '0';
            VARIABLE TD_CENegIn_CLK      : VitalTimingDataType;

            VARIABLE Tviol_CE2NegIn_CLK  : X01 := '0';
            VARIABLE TD_CE2NegIn_CLK     : VitalTimingDataType;

            VARIABLE Tviol_CE2In_CLK     : X01 := '0';
            VARIABLE TD_CE2In_CLK        : VitalTimingDataType;

            VARIABLE Pviol_CLK    : X01 := '0';
            VARIABLE PD_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE MemAddr    : NATURAL RANGE 0 TO MemSize;
            VARIABLE startaddr  : NATURAL RANGE 0 TO MemSize;

            VARIABLE Burst_Cnt  : NATURAL RANGE 0 TO 4 := 0;
            VARIABLE memstart   : NATURAL RANGE 0 TO 3 := 0;
            VARIABLE offset     : INTEGER RANGE -3 TO 3 := 0;

            VARIABLE command    : command_type;
            VARIABLE R          : std_logic;

            VARIABLE zz_set     : BOOLEAN := false;
            VARIABLE zz_reset   : BOOLEAN := true;
            VARIABLE zz_cnt     : INTEGER RANGE 0 TO 2 := 0;

        BEGIN

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_A0_CLK,
                    SetupLow        => tsetup_A0_CLK,
                    HoldHigh        => thold_A0_CLK,
                    HoldLow         => thold_A0_CLK,
                    CheckEnabled    => (ZZIn = '0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_AddressIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_AddressIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DatBIn,
                    TestSignalName  => "DatB",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQA0_CLK,
                    SetupLow        => tsetup_DQA0_CLK,
                    HoldHigh        => thold_DQA0_CLK,
                    HoldLow         => thold_DQA0_CLK,
                    CheckEnabled    => (ZZIn ='0') AND
                                       (DatBIn/=D_zd(17 downto 9)),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DatBIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DatBIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DatAIn,
                    TestSignalName  => "DatA",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQA0_CLK,
                    SetupLow        => tsetup_DQA0_CLK,
                    HoldHigh        => thold_DQA0_CLK,
                    HoldLow         => thold_DQA0_CLK,
                    CheckEnabled    => (ZZIn ='0') AND
                                       (DatAIn/=D_zd(8 downto 0)),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DatAIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DatAIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => GWNIn,
                    TestSignalName  => "GW",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_BWANeg_CLK,
                    SetupLow        => tsetup_BWANeg_CLK,
                    HoldHigh        => thold_BWANeg_CLK,
                    HoldLow         => thold_BWANeg_CLK,
                    CheckEnabled    => (ZZIn ='0'),