idt71421.vhd

vhdl cod for ram.For sp3e

                            Pviol_AL7              OR
                            Pviol_AL8              OR
                            Pviol_AL9              OR
                            Pviol_AL10             OR
                            Pviol_AR0              OR
                            Pviol_AR1              OR
                            Pviol_AR2              OR
                            Pviol_AR3              OR
                            Pviol_AR4              OR
                            Pviol_AR5              OR
                            Pviol_AR6              OR
                            Pviol_AR7              OR
                            Pviol_AR8              OR
                            Pviol_AR9              OR
                            Pviol_AR10             OR
                            Pviol_CELNeg           OR
                            Pviol_CERNeg           OR
                            Pviol_RWL              OR
                            Pviol_RWR;
            ASSERT Violation = '0'
            REPORT InstancePath & partID &
             " simulation may be inaccurate due to timing violations"
            SEVERITY WARNING;

            viol <= violation;
        END IF; -- TimingChecksOn
        END PROCESS VITALTimingCheck;
        --------------------------------------------------------------------
        -- Control Process
        --------------------------------------------------------------------
        SRAM_COMMAND : PROCESS(CELNeg, OELNeg, RWL, CERNeg, OERNeg,
        RWR, ALIn, ARIn)
        BEGIN
            RRead  <= '0';
            LRead  <= '0';
            RWrite <= '0';
            LWrite <= '0';
            IF CELNeg = '0' THEN
                IF RWL = '0' THEN
                    IF BUSYLNeg /= '0'THEN
                        LWrite <= '1';
                    ELSE
                        LWrite <= '0';
                    END IF;
                ELSIF RWL = '1' AND  OELNeg = '0' THEN
                    LRead  <= '1';
                END IF;
            END IF;
            IF CERNeg = '0' THEN
                IF RWR = '0' THEN
                    IF BUSYRNeg /= '0'THEN
                        RWrite <= '1';
                    ELSE
                        RWrite <= '0';
                    END IF;
                ELSIF RWR = '1' AND  OERNeg = '0' THEN
                    RRead  <= '1';
                END IF;
            END IF;
        END PROCESS SRAM_COMMAND;

        --------------------------------------------------------------------
        -- Write Process
        --------------------------------------------------------------------
        ToggleW : PROCESS(RWR, RWL)
        BEGIN
            IF falling_edge(RWR) THEN
                ToggleWR <= NOT ToggleWR;
            END IF;
            IF falling_edge(RWL) THEN
                ToggleWL <= NOT ToggleWL;
            END IF;
        END PROCESS ToggleW;
        -- delay 1 ns because hold time is 0 ns for write cycle
        ALIn_t  <= ALIn AFTER 1 ns;
        ARIn_t  <= ARIn AFTER 1 ns;
        IOLIn_t <= IOLIn AFTER 1 ns;
        IORIn_t <= IORIn AFTER 1 ns;
        WriteP : PROCESS(LWrite, RWrite)
            VARIABLE Address : INTEGER RANGE 0 TO TotalLOC:= 0;
            VARIABLE Data    : INTEGER RANGE 0 TO MaxData:= 0;
            VARIABLE tDD     : TIME := 0 ns;
            VARIABLE tWD     : TIME := 0 ns;
        BEGIN
            IF falling_edge(LWrite) THEN
                Address := to_nat(ALIn_t);
                Data    := to_nat(IOLIn_t);
                MemData(Address) := Data;
                IF Address = 16#7FF# AND InterruptEnable THEN
                    SetIntR     <= '1', '0' AFTER 1 ns;
                END IF;
                IF BUSYRNeg = '0' THEN
                    tDD := -IOLIn'LAST_EVENT     + tdevice_TDDD;
                    tWD := -ToggleWL'LAST_EVENT  + tdevice_TWDD;
                    IF tDD >= tWD AND tDD > 0 ns THEN
                        reinvoke <= '1' AFTER tDD, '0' AFTER tDD + 1 ns;
                    ELSIF tWD >= tWD AND tWD > 0 ns THEN
                        reinvoke <= '1' AFTER tWD, '0' AFTER tWD + 1 ns;
                    ELSE
                        reinvoke <= '1', '0' AFTER 1 ns;
                    END IF;
                END IF;
            END IF;
            IF falling_edge(RWrite) THEN
                Address := to_nat(ARIn_t);
                Data    := to_nat(IORIn_t);
                MemData(Address) := Data;
                IF Address = 16#7FE# AND InterruptEnable THEN
                    SetIntL     <= '1', '0' AFTER 1 ns;
                END IF;
                IF BUSYLNeg = '0' THEN
                    tDD := -IORIn'LAST_EVENT     + tdevice_TDDD;
                    tWD := -ToggleWR'LAST_EVENT  + tdevice_TWDD;
                    IF tDD >= tWD AND tDD > 0 ns THEN
                        reinvoke <= '1' AFTER tDD, '0' AFTER tDD + 1 ns;
                    ELSIF tWD >= tWD AND tWD > 0 ns THEN
                        reinvoke <= '1' AFTER tWD, '0' AFTER tWD + 1 ns;
                    ELSE
                        reinvoke <= '1', '0' AFTER 1 ns;
                    END IF;
                END IF;
            END IF;
        END PROCESS WriteP;

        --------------------------------------------------------------------
        -- Read Process
        --------------------------------------------------------------------
        ReadL : PROCESS(LRead, ALIn, reinvoke)
            VARIABLE Address : INTEGER := 0;
            VARIABLE Data    : INTEGER := 0;
        BEGIN
            IF LRead = '1' THEN
                Address := to_nat(ALIn);
                IOL_zd <= to_slv(MemData(Address), DataWidth);
                IF Address = 16#7FE# THEN
                    ClearIntL     <= '1', '0' AFTER 1 ns;
                END IF;
            ELSE
                IOL_zd <= (OTHERS => 'Z');
            END IF;
        END PROCESS ReadL;

        ReadR : PROCESS(RRead, ARIn, reinvoke)
            VARIABLE Address : INTEGER := 0;
            VARIABLE Data    : INTEGER := 0;
        BEGIN
            IF RRead = '1' THEN
                Address := to_nat(ARIn);
                IOR_zd <= to_slv(MemData(Address), DataWidth);
                IF Address = 16#7FF# THEN
                    ClearIntR     <= '1', '0' AFTER 1 ns;
                END IF;
            ELSE
                IOR_zd <= (OTHERS => 'Z');
            END IF;
        END PROCESS ReadR;

        ----------------------------------------------------------------------
        ---- Interrupt section
        ----------------------------------------------------------------------
        InterruptProc : PROCESS(ClearIntR, ClearIntL, SetIntR, SetIntL)
        BEGIN
            IF rising_edge(SetIntR) THEN
                INTRNeg_zd <= '0';
            END IF;
            IF rising_edge(SetIntL) THEN
                INTLNeg_zd <= '0';
            END IF;
            IF rising_edge(ClearIntL) THEN
                INTLNeg_zd <= '1';
            END IF;
            IF rising_edge(ClearIntR) THEN
                INTRNeg_zd <= '1';
            END IF;
        END PROCESS InterruptProc;

        -----------------------------------------------------------------------
        ---- File read Section - Preload Control
        -----------------------------------------------------------------------
        MemPreload : PROCESS
            -- text file input variables
            FILE     mem_f         : text  is  mem_file_name;
            VARIABLE addr_ind      : NATURAL;
            VARIABLE buf           : line;
            VARIABLE line          : NATURAL :=0;
            VARIABLE report_err    : BOOLEAN := FALSE;

        BEGIN
        ----------------------------------------------------------------------
        -- idt71421  memory preload file format
        --   /       - comment
        --   @aaa    - <aaa> stands for address within sector
        --   dd      - <dd> is word to be written at Mem(aaa++)
        --             (aaa is incremented at every load)
        --   only first 1-4 columns are loaded. NO empty lines !!!!!!!!!!!!!!!!
        ----------------------------------------------------------------------
            IF UserPreload AND (mem_file_name /= "none" ) THEN
                MemData := (OTHERS => 0);
                addr_ind   := 0;
                WHILE (not ENDFILE (mem_f)) LOOP
                    READLINE (mem_f, buf);
                    line := line +1;
                    IF buf(1) = '/' THEN
                        NEXT;
                    ELSIF buf(1) = '@' THEN
                        addr_ind := h(buf(2  to 4));
                    ELSE
                        IF addr_ind <= TotalLOC THEN
                            MemData(addr_ind):= h(buf(1 to 2));
                            addr_ind := (addr_ind + 1);
                        ELSE
                            IF report_err = FALSE THEN
                                REPORT "Memory file:" & mem_file_name &
                                    " Address range overflow"&
                                    " at line "&to_int_str(line)
                                SEVERITY warning;
                                report_err := TRUE;
                            END IF;
                        END IF;
                    END IF;
                 END LOOP;
            END IF;
            WAIT;
        END PROCESS;

        IOLPassThrough : PROCESS(IOL_zd)
            VARIABLE tOLD  : time := 0 ns;
            VARIABLE tCLD  : time := 0 ns;
            VARIABLE tALD  : time := 0 ns;
            VARIABLE IOL_x : std_logic_vector(HiDbit DOWNTO 0);
        BEGIN
        IOL_x   := (OTHERS => 'X');
        IF IOL_zd(0) /= 'Z' THEN
            tpd_OEL := FALSE;
            tpd_CEL := FALSE;
            tOLD := -OELNeg'LAST_EVENT   + tpd_OELNeg_IOL0(trz1);
            tCLD := -CELNeg'LAST_EVENT   + tpd_CELNeg_IOL0(trz1);
            tALD := -ALIn'LAST_EVENT     + tpd_AL0_IOL0(tr01);
            IF tOLD >= tCLD AND tOLD > 0 ns THEN
                tpd_OEL := TRUE;
            ELSIF tCLD >= tOLD AND tCLD > 0 ns THEN
                tpd_CEL := TRUE;
            END IF;
            IF tALD > 0 ns AND
                ((tALD >= tOLD AND tpd_OEL  = TRUE) OR
                (tALD >= tCLD AND tpd_CEL  = TRUE)) THEN
                IOL_pass <= IOL_x, IOL_zd AFTER tALD;
            ELSE
                IOL_pass <= IOL_zd;
            END IF;
        ELSE
            tpd_OEL := TRUE;
            tpd_CEL := TRUE;
            IOL_Pass <= IOL_zd;
        END IF;
        END PROCESS IOLPassThrough;

        IORPassThrough : PROCESS(IOR_zd)
            VARIABLE tORD  : time := 0 ns;
            VARIABLE tCRD  : time := 0 ns;
            VARIABLE tARD  : time := 0 ns;
            VARIABLE IOR_x : std_logic_vector(HiDbit DOWNTO 0);
        BEGIN
        IOR_x   := (OTHERS => 'X');
        IF IOR_zd(0) /= 'Z' THEN
            tpd_OER := FALSE;
            tpd_CER := FALSE;
            tORD := -OERNeg'LAST_EVENT   + tpd_OELNeg_IOL0(trz1);
            tCRD := -CERNeg'LAST_EVENT   + tpd_CELNeg_IOL0(trz1);
            tARD := -ARIn'LAST_EVENT     + tpd_AL0_IOL0(tr01);
            IF tORD >= tCRD AND tORD > 0 ns THEN
                tpd_OER := TRUE;
            ELSIF tCRD >= tORD AND tCRD > 0 ns THEN
                tpd_CER := TRUE;
            END IF;
            IF tARD > 0 ns AND
                ((tARD >= tORD AND tpd_OER  = TRUE) OR
                (tARD >= tCRD AND tpd_CER  = TRUE)) THEN
                IOR_pass <= IOR_x, IOR_zd AFTER tARD;
            ELSE
                IOR_pass <= IOR_zd;
            END IF;
        ELSE
            tpd_OER := TRUE;
            tpd_CER := TRUE;
            IOR_Pass <= IOR_zd;
        END IF;
        END PROCESS IORPassThrough;

        -----------------------------------------------------------------------
        -- Path Delay Section for Interrupt
        -----------------------------------------------------------------------
        INTL_OUT: PROCESS(INTLNeg_zd)
            VARIABLE INTLNeg_GlitchData : VitalGlitchDataType;
            VARIABLE INT_var            : std_logic := 'Z';
        BEGIN
            IF INTLNeg_zd = '0' THEN
                INT_var  := '0';
            ELSE
                INT_var  := 'Z';
            END IF;
            VitalPathDelay01Z(