📄 idt71v65603.ftm

📁 vhdl cod for ram.For sp3e
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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for IDT71V65603 Parts</TITLE><REVISION.HISTORY>version: |  author:  | mod date: | changes made:  V1.0     R. Munden   00 JUL 25   Initial release  V1.1     R. Munden   01 NOV 19   Added 20 new part numbers</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>IDT71V65603<FMFTIME>IDT71V65603S150BG<SOURCE>IDT Datasheet DSC-5304/01 Rev. October 2001</SOURCE>IDT71V65603S150BQ<SOURCE>IDT Datasheet DSC-5304/01 Rev. October 2001</SOURCE>IDT71V65603S150PF<SOURCE>IDT Datasheet DSC-5304/01 Rev. October 2001</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:3.0:3.8) (1.5:3.0:3.8) (1.5:2.6:3.0) (1.5:3.0:3.8) (1.5:2.6:3.0) (1.5:3.0:3.8))     (IOPATH OENeg DQA0 () () (0.0:3.0:3.8) (0.0:3.0:3.8) (0.0:3.0:3.8) (0.0:3.0:3.8))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (2.0))    (WIDTH  (negedge CLK) (2.0))    (PERIOD (posedge CLK) (6.7))    (SETUP CLKENNeg CLK (1.5))    (SETUP A0 CLK (1.5))    (SETUP DQA0 CLK (1.5))    (SETUP R CLK (1.5))    (SETUP ADV CLK (1.5))    (SETUP CE2 CLK (1.5))    (SETUP BWANeg CLK (1.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V65603S133BG<SOURCE>IDT Datasheet DSC-5304/01 Rev. October 2001</SOURCE>IDT71V65603S133BQ<SOURCE>IDT Datasheet DSC-5304/01 Rev. October 2001</SOURCE>IDT71V65603S133PF<SOURCE>IDT Datasheet DSC-5304/01 Rev. October 2001</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:3.3:4.2) (1.5:3.3:4.2) (1.5:2.6:3.0) (1.5:3.4:4.2) (1.5:2.6:3.0) (1.5:3.4:4.2))     (IOPATH OENeg DQA0 () () (0.0:3.6:4.2) (0.0:3.6:4.2) (0.0:3.6:4.2) (0.0:3.6:4.2))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (2.2))    (WIDTH  (negedge CLK) (2.2))    (PERIOD (posedge CLK) (7.5))    (SETUP CLKENNeg CLK (1.7))    (SETUP A0 CLK (1.7))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (1.7))    (SETUP ADV CLK (1.7))    (SETUP CE2 CLK (1.7))    (SETUP BWANeg CLK (1.7))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V65603S100BG<SOURCE>IDT Datasheet DSC-5304/01 Rev. October 2001</SOURCE>IDT71V65603S100BQ<SOURCE>IDT Datasheet DSC-5304/01 Rev. October 2001</SOURCE>IDT71V65603S100PF<SOURCE>IDT Datasheet DSC-5304/01 Rev. October 2001</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:3.8:5.0) (1.5:3.8:5.0) (1.5:2.4:3.3) (1.5:3.8:5.0) (1.5:2.4:3.3) (1.5:3.8:5.0))     (IOPATH OENeg DQA0 () () (0.0:3.0:5.0) (0.0:3.0:5.0) (0.0:3.0:5.0) (0.0:3.0:5.0))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (3.2))    (WIDTH  (negedge CLK) (3.2))    (PERIOD (posedge CLK) (10.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP A0 CLK (2.0))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MT55L256L36PB-10<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256L36PF-10<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256L36PT-10<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256V36PB-10<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256V36PF-10<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256V36PT-10<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE><COMMENT> The values listed are for VCC=3.3V, CL=50pF, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.5:3:5) (1.5:3:5) (1.5:2.5:3.5) (1.5:3:5) (1.5:2.5:3.5) (1.5:3:5))    (IOPATH OENeg DQA0 () () (1.5:3:5) (0:3:5) (1.5:3:5) (0:3:5))  ))  (TIMINGCHECK    (SETUP CLKENNeg CLK (2:2:2))    (SETUP A0 CLK (2:2:2))    (SETUP DQA0 CLK (2:2:2))    (SETUP R CLK (2:2:2))    (SETUP ADV CLK (2:2:2))    (SETUP CE2 CLK (2:2:2))    (SETUP BWANeg CLK (2:2:2))    (HOLD CLKENNeg CLK (.5:.5:.5))    (HOLD A0 CLK (.5:.5:.5))    (HOLD DQA0 CLK (.5:.5:.5))    (HOLD R CLK (.5:.5:.5))    (HOLD ADV CLK (.5:.5:.5))    (HOLD CE2 CLK (.5:.5:.5))    (HOLD BWANeg CLK (.5:.5:.5))    (WIDTH (posedge CLK) (3.2:3.2:3.2))    (WIDTH (negedge CLK) (3.2:3.2:3.2))    (PERIOD (posedge CLK) (10:10:10))  )</TIMING></FMFTIME><FMFTIME>MT55L256L36PB-7.5<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256L36PF-7.5<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256L36PT-7.5<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256V36PB-7.5<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256V36PF-7.5<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256V36PT-7.5<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE><COMMENT> The values listed are for VCC=3.3V, CL=50pF, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.5:2.8:4.2) (1.5:2.8:4.2) (1.5:2.5:3.5) (1.5:2.8:4.2) (1.5:2.5:3.5) (1.5:2.8:4.2))    (IOPATH OENeg DQA0 () () (1.5:2.8:4.2) (0:2.8:4.2) (1.5:2.8:4.2) (0:2.8:4.2))  ))  (TIMINGCHECK    (SETUP CLKENNeg CLK (1.7:1.7:1.7))    (SETUP A0 CLK (1.7:1.7:1.7))    (SETUP DQA0 CLK (1.7:1.7:1.7))    (SETUP R CLK (1.7:1.7:1.7))    (SETUP ADV CLK (1.7:1.7:1.7))    (SETUP CE2 CLK (1.7:1.7:1.7))    (SETUP BWANeg CLK (1.7:1.7:1.7))    (HOLD CLKENNeg CLK (.5:.5:.5))    (HOLD A0 CLK (.5:.5:.5))    (HOLD DQA0 CLK (.5:.5:.5))    (HOLD R CLK (.5:.5:.5))    (HOLD ADV CLK (.5:.5:.5))    (HOLD CE2 CLK (.5:.5:.5))    (HOLD BWANeg CLK (.5:.5:.5))    (WIDTH (posedge CLK) (2:2:2))    (WIDTH (negedge CLK) (2:2:2))    (PERIOD (posedge CLK) (7.5:7.5:7.5))  )</TIMING></FMFTIME><FMFTIME>MT55L256L36PB-6<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256L36PF-6<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256L36PT-6<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256V36PB-6<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256V36PF-6<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE>MT55L256V36PT-6<SOURCE>Micron Technology MT55L512L18P_2.p65 - Rev. 6/01</SOURCE><COMMENT> The values listed are for VCC=3.3V, CL=50pF, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.5:2.5:3.5) (1.5:2.5:3.5) (1.5:2.5:3.5) (1.5:2.5:3.5) (1.5:2.5:3.5) (1.5:2.5:3.5))    (IOPATH OENeg DQA0 () () (1.5:2.5:3.5) (0:2.5:3.5) (1.5:2.5:3.5) (0:2.5:3.5))  ))  (TIMINGCHECK    (SETUP CLKENNeg CLK (1.5:1.5:1.5))    (SETUP A0 CLK (1.5:1.5:1.5))    (SETUP DQA0 CLK (1.5:1.5:1.5))    (SETUP R CLK (1.5:1.5:1.5))    (SETUP ADV CLK (1.5:1.5:1.5))    (SETUP CE2 CLK (1.5:1.5:1.5))    (SETUP BWANeg CLK (1.5:1.5:1.5))    (HOLD CLKENNeg CLK (.5:.5:.5))    (HOLD A0 CLK (.5:.5:.5))    (HOLD DQA0 CLK (.5:.5:.5))    (HOLD R CLK (.5:.5:.5))    (HOLD ADV CLK (.5:.5:.5))    (HOLD CE2 CLK (.5:.5:.5))    (HOLD BWANeg CLK (.5:.5:.5))    (WIDTH (posedge CLK) (1.7:1.7:1.7))    (WIDTH (negedge CLK) (1.7:1.7:1.7))    (PERIOD (posedge CLK) (6:6:6))  )</TIMING></FMFTIME><FMFTIME>CY7C1354A-100AC<SOURCE>Cypress Semiconductor Data Sheet May 18, 2000</SOURCE>CY7C1354A-100BGC<SOURCE>Cypress Semiconductor Data Sheet May 18, 2000</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1:3.4:5) (1:3.4:5) (1:2:3) (1:3.4:5) (1:2:3) (1:3.4:5))    (IOPATH OENeg DQA0 () () (1:2.3:3.5) (0:3.4:5) (1:2.3:3.5) (0:3.4:5))  ))  (TIMINGCHECK    (SETUP CLKENNeg CLK (2:2:2))    (SETUP A0 CLK (2:2:2))    (SETUP DQA0 CLK (2:2:2))    (SETUP R CLK (2:2:2))    (SETUP ADV CLK (2:2:2))    (SETUP CE2 CLK (2:2:2))    (SETUP BWANeg CLK (2:2:2))    (HOLD CLKENNeg CLK (.5:.5:.5))    (HOLD A0 CLK (.5:.5:.5))    (HOLD DQA0 CLK (.5:.5:.5))    (HOLD R CLK (.5:.5:.5))    (HOLD ADV CLK (.5:.5:.5))    (HOLD CE2 CLK (.5:.5:.5))    (HOLD BWANeg CLK (.5:.5:.5))    (WIDTH (posedge CLK) (3.5:3.5:3.5))    (WIDTH (negedge CLK) (3.5:3.5:3.5))    (PERIOD (posedge CLK) (10:10:10))  )</TIMING></FMFTIME><FMFTIME>CY7C1354A-133AC<SOURCE>Cypress Semiconductor Data Sheet May 18, 2000</SOURCE>CY7C1354A-133BGC<SOURCE>Cypress Semiconductor Data Sheet May 18, 2000</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1:2.8:4.2) (1:2.8:4.2) (1:2:3) (1:2.8:4.2) (1:2:3) (1:2.8:4.2))    (IOPATH OENeg DQA0 () () (1:2.3:3.5) (0:2.8:4.2) (1:2.3:3.5) (0:2.8:4.2))  ))  (TIMINGCHECK    (SETUP CLKENNeg CLK (1.8:1.8:1.8))    (SETUP A0 CLK (1.8:1.8:1.8))    (SETUP DQA0 CLK (1.8:1.8:1.8))    (SETUP R CLK (1.8:1.8:1.8))    (SETUP ADV CLK (1.8:1.8:1.8))    (SETUP CE2 CLK (1.8:1.8:1.8))    (SETUP BWANeg CLK (1.8:1.8:1.8))    (HOLD CLKENNeg CLK (.5:.5:.5))    (HOLD A0 CLK (.5:.5:.5))    (HOLD DQA0 CLK (.5:.5:.5))    (HOLD R CLK (.5:.5:.5))    (HOLD ADV CLK (.5:.5:.5))    (HOLD CE2 CLK (.5:.5:.5))    (HOLD BWANeg CLK (.5:.5:.5))    (WIDTH (posedge CLK) (2.6:2.6:2.6))    (WIDTH (negedge CLK) (2.6:2.6:2.6))    (PERIOD (posedge CLK) (7.5:7.5:7.5))  )</TIMING></FMFTIME><FMFTIME>CY7C1354A-166AC<SOURCE>Cypress Semiconductor Data Sheet May 18, 2000</SOURCE>CY7C1354A-166BGC<SOURCE>Cypress Semiconductor Data Sheet May 18, 2000</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1:2.4:3.6) (1:2.4:3.6) (1:2:3) (1:2.4:3.6) (1:2:3) (1:2.4:3.6))    (IOPATH OENeg DQA0 () () (1:2.3:3.5) (0:2.4:3.6) (1:2.3:3.5) (0:2.4:32.6))  ))  (TIMINGCHECK    (SETUP CLKENNeg CLK (1.5:1.5:1.5))    (SETUP A0 CLK (1.5:1.5:1.5))    (SETUP DQA0 CLK (1.5:1.5:1.5))    (SETUP R CLK (1.5:1.5:1.5))    (SETUP ADV CLK (1.5:1.5:1.5))    (SETUP CE2 CLK (1.5:1.5:1.5))    (SETUP BWANeg CLK (1.5:1.5:1.5))    (HOLD CLKENNeg CLK (.5:.5:.5))    (HOLD A0 CLK (.5:.5:.5))    (HOLD DQA0 CLK (.5:.5:.5))    (HOLD R CLK (.5:.5:.5))    (HOLD ADV CLK (.5:.5:.5))    (HOLD CE2 CLK (.5:.5:.5))    (HOLD BWANeg CLK (.5:.5:.5))    (WIDTH (posedge CLK) (2.1:2.1:2.1))    (WIDTH (negedge CLK) (2.1:2.1:2.1))    (PERIOD (posedge CLK) (6:6:6))  )</TIMING></FMFTIME><FMFTIME>CY7C1354A-200AC<SOURCE>Cypress Semiconductor Data Sheet May 18, 2000</SOURCE>CY7C1354A-200BGC<SOURCE>Cypress Semiconductor Data Sheet May 18, 2000</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1:2.1:3.2) (1:2.1:3.2) (1:2:3) (1:2.1:3.2) (1:2:3) (1:2.1:3.2))    (IOPATH OENeg DQA0 () () (1:2.3:3.5) (0:2.1:3.2) (1:2.3:3.5) (0:2.1:3.2))  ))  (TIMINGCHECK    (SETUP CLKENNeg CLK (1.5:1.5:1.5))    (SETUP A0 CLK (1.5:1.5:1.5))    (SETUP DQA0 CLK (1.5:1.5:1.5))    (SETUP R CLK (1.5:1.5:1.5))    (SETUP ADV CLK (1.5:1.5:1.5))    (SETUP CE2 CLK (1.5:1.5:1.5))    (SETUP BWANeg CLK (1.5:1.5:1.5))    (HOLD CLKENNeg CLK (.5:.5:.5))    (HOLD A0 CLK (.5:.5:.5))    (HOLD DQA0 CLK (.5:.5:.5))    (HOLD R CLK (.5:.5:.5))    (HOLD ADV CLK (.5:.5:.5))    (HOLD CE2 CLK (.5:.5:.5))    (HOLD BWANeg CLK (.5:.5:.5))    (WIDTH (posedge CLK) (1.8:1.8:1.8))    (WIDTH (negedge CLK) (1.8:1.8:1.8))    (PERIOD (posedge CLK) (5:5:5))  )</TIMING></FMFTIME></BODY></FTML>
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