mt46v32m8.vhd

vhdl cod for ram.For sp3e

            VARIABLE Tviol_DQS_CLK       : X01 := '0';
            VARIABLE TD_DQS_CLK          : VitalTimingDataType;

            VARIABLE Tviol_CKE_CLK      : X01 := '0';
            VARIABLE TD_CKE_CLK         : VitalTimingDataType;

            VARIABLE Tviol_Address_CLK  : X01 := '0';
            VARIABLE TD_Address_CLK     : VitalTimingDataType;

            VARIABLE Tviol_WENeg_CLK    : X01 := '0';
            VARIABLE TD_WENeg_CLK       : VitalTimingDataType;

            VARIABLE Tviol_RASNeg_CLK   : X01 := '0';
            VARIABLE TD_RASNeg_CLK      : VitalTimingDataType;

            VARIABLE Tviol_CSNeg_CLK    : X01 := '0';
            VARIABLE TD_CSNeg_CLK       : VitalTimingDataType;

            VARIABLE Tviol_CASNeg_CLK   : X01 := '0';
            VARIABLE TD_CASNeg_CLK      : VitalTimingDataType;

            VARIABLE Tviol_D0_DQS       : X01 := '0';
            VARIABLE TD_D0_DQS          : VitalTimingDataType;

            VARIABLE Tviol_DM_DQS      : X01 := '0';
            VARIABLE TD_DM_DQS         : VitalTimingDataType;

            VARIABLE Pviol_CLK     : X01 := '0';
            VARIABLE PD_CLK        : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_DQS     : X01 := '0';
            VARIABLE PD_DQS        : VitalPeriodDataType := VitalPeriodDataInit;

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to depth) OF INTEGER
                             RANGE  -2 TO 255;

            TYPE MemBlock IS ARRAY (0 to 3) OF MemStore;
            TYPE mode_set_type IS (standard, extended);
            TYPE Burst_type IS (sequential, interleave);
            TYPE Write_Burst_type IS (programmed, single);
            TYPE sequence IS ARRAY (0 to 7) OF NATURAL RANGE 0 to 7;
            TYPE seqtab IS ARRAY (0 to 7) OF sequence;
            TYPE MemLoc IS ARRAY (0 to 3) OF
                 std_logic_vector(HiAddrBit+HiColBit+1 DOWNTO 0);
            TYPE burst_counter IS ARRAY (0 to 3) OF NATURAL RANGE 0 to 257;
            TYPE StartAddr_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO 7;
            TYPE Burst_Inc_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO 8;
            TYPE BaseLoc_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO depth;
            SUBTYPE OutWord IS std_logic_vector(7 DOWNTO 0);

            CONSTANT seq0 : sequence := (0 & 1 & 2 & 3 & 4 & 5 & 6 & 7);
            CONSTANT seq1 : sequence := (1 & 0 & 3 & 2 & 5 & 4 & 7 & 6);
            CONSTANT seq2 : sequence := (2 & 3 & 0 & 1 & 6 & 7 & 4 & 5);
            CONSTANT seq3 : sequence := (3 & 2 & 1 & 0 & 7 & 6 & 5 & 4);
            CONSTANT seq4 : sequence := (4 & 5 & 6 & 7 & 0 & 1 & 2 & 3);
            CONSTANT seq5 : sequence := (5 & 4 & 7 & 6 & 1 & 0 & 3 & 2);
            CONSTANT seq6 : sequence := (6 & 7 & 4 & 5 & 2 & 3 & 0 & 1);
            CONSTANT seq7 : sequence := (7 & 6 & 5 & 4 & 3 & 2 & 1 & 0);
            CONSTANT intab : seqtab := (seq0, seq1, seq2, seq3, seq4, seq5,
                                        seq6, seq7);

            FILE mem_file       : text IS  mem_file_name;
            VARIABLE MemData    : MemBlock;
            VARIABLE file_bank  : NATURAL := 0;
            VARIABLE ind        : NATURAL := 0;
            VARIABLE buf        : line;
            VARIABLE mode_set_ind : mode_set_type ;

            VARIABLE MemAddr      : MemLoc;
            VARIABLE Location     : NATURAL RANGE 0 TO depth := 0;
            VARIABLE Location2    : NATURAL RANGE 0 TO depth := 0;
            VARIABLE BaseLoc      : BaseLoc_type;
            VARIABLE Burst_Inc    : Burst_Inc_type;
            VARIABLE StartAddr    : StartAddr_type;

            VARIABLE Burst_Length : NATURAL RANGE 2 TO 8 := 2;
            VARIABLE Burst_Bits   : NATURAL RANGE 1 TO 3 := 1;
            VARIABLE Burst        : Burst_Type;
            VARIABLE Burst_Cnt    : burst_counter;

            VARIABLE command    : command_type;
            VARIABLE written    : boolean := false;
            VARIABLE chip_en    : boolean := false;
            VARIABLE write_to_write : boolean := false;
            VARIABLE DQS_event_reg : boolean := false;

            VARIABLE cur_bank   : natural range 0 to hi_bank;

            VARIABLE ModeReg    : std_logic_vector(12 DOWNTO 0)
                                   := (OTHERS => 'X');
            VARIABLE ExtModeReg    : std_logic_vector(12 DOWNTO 0)
                                   := (OTHERS => 'X');

            VARIABLE Ref_Cnt      : NATURAL RANGE 0 TO 8192 := 0;
            VARIABLE next_ref     : TIME;
            VARIABLE BankString   : STRING(8 DOWNTO 1) := " Bank-X ";

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';
            VARIABLE DataDriveOut :  std_logic_vector(7 DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataDrive  : OutWord;
            VARIABLE DataDrive1 : OutWord;
            VARIABLE DataDrive2 : OutWord;
            VARIABLE DataDrive3 : OutWord;
            VARIABLE DataDrive4 : OutWord;
            VARIABLE DataDrive5 : OutWord;
            VARIABLE DataDrive6 : OutWord;
            VARIABLE DM_reg0  : UX01;
            VARIABLE DM_reg1  : UX01;
            VARIABLE DM_reg2  : UX01;

            VARIABLE DQSDriveOut : std_logic;
            VARIABLE DQSDrive  : std_logic;
            VARIABLE DQSDrive1 : std_logic;
            VARIABLE DQSDrive2 : std_logic;
            VARIABLE DQSDrive3 : std_logic;
            VARIABLE DQSDrive4 : std_logic;
            VARIABLE DQSDrive5 : std_logic;
            VARIABLE DQSDrive6 : std_logic;
            VARIABLE DQSDrive7 : std_logic;
            VARIABLE DQS_zd    : std_logic;
            VARIABLE DQS_GlitchData : VitalGlitchDataType;

            VARIABLE InputReg  :INTEGER RANGE  -2 TO 255;

        PROCEDURE FixColumnAddress( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
           MemAddr(bank)(HiColBit downto 0) := (others => '0');
           MemAddr(bank)(HiColBit downto Burst_Bits) :=
                      AddressIn(HiColBit downto Burst_Bits); --

           Burst_Inc(bank) := to_nat(AddressIn(Burst_Bits-1 downto 0));
           StartAddr(bank) := Burst_Inc(bank) mod 8;
           BaseLoc(bank) := to_nat(MemAddr(bank));
           Location := BaseLoc(bank) + Burst_Inc(bank);
        END PROCEDURE ;

        PROCEDURE ReadFromMem( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            DQSDrive:='0';

            IF MemData(Bank)(Location) = -2 THEN
                DataDrive(HiDataBit downto 0) := (others => 'U');
            ELSIF MemData(Bank)(Location) = -1 THEN
                DataDrive(HiDataBit downto 0) := (others => 'X');
            ELSE
                DataDrive(HiDataBit downto 0):=
                    to_slv(MemData(Bank)(Location),HiDataBit+1);
            END IF;
        END;

        PROCEDURE WriteToMem( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            IF DQS_event_reg THEN
                IF Violation = '0' THEN
                    MemData(Bank)(Location) := InputReg;
                ELSE
                    MemData(Bank)(Location) := -1;
                END IF;
            END IF;
        END;

        PROCEDURE BurstCtrl( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            IF (Burst = sequential) THEN
                Burst_Inc(bank) := (Burst_Inc(bank) + 1) MOD
                                    Burst_Length;
            ELSE
                Burst_Inc(bank) := intab(StartAddr(bank))
                                        (Burst_Cnt(bank));
            END IF;
        END;

        BEGIN

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => BAIn,
                    TestSignalName  => "BA",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQ0_CLK,
                    SetupLow        => tsetup_DQ0_CLK,
                    HoldHigh        => thold_DQ0_CLK,
                    HoldLow         => thold_DQ0_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_BA_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_BA_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DMIn,
                    TestSignalName  => "DM",
                    RefSignal       => DQSIn,
                    RefSignalName   => "DQS",
                    SetupHigh       => tsetup_DM_DQS,
                    SetupLow        => tsetup_DM_DQS,
                    HoldHigh        => thold_DM_DQS,
                    HoldLow         => thold_DM_DQS,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DM_DQS,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DM_DQS );

                VitalSetupHoldCheck (
                    TestSignal      => DataIn,
                    TestSignalName  => "Data",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQ0_CLK,
                    SetupLow        => tsetup_DQ0_CLK,
                    HoldHigh        => thold_DQ0_CLK,
                    HoldLow         => thold_DQ0_CLK,
                    CheckEnabled    => chip_en AND
                                        NOT(DataIn(0)='X' AND D_zd(0)='Z'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D0_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D0_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DataIn,
                    TestSignalName  => "Data",
                    RefSignal       => DQSIn,
                    RefSignalName   => "DQS",
                    SetupHigh       => tsetup_DQ0_DQS,
                    SetupLow        => tsetup_DQ0_DQS,
                    HoldHigh        => thold_DQ0_DQS,
                    HoldLow         => thold_DQ0_DQS,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D0_DQS,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D0_DQS );

                VitalSetupHoldCheck (
                    TestSignal      => DQSIn,
                    TestSignalName  => "DQS",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQS_CLK,
                    HoldHigh        => thold_DQS_CLK,
                    CheckEnabled    => chip_en AND (NOT DQSIn=DQS_zd),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DQS_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DQS_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => CKEIn,
                    TestSignalName  => "CKE",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQ0_CLK,
                    SetupLow        => tsetup_DQ0_CLK,
                    HoldHigh        => thold_DQ0_CLK,
                    HoldLow         => thold_DQ0_CLK,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CKE_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CKE_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_A0_CLK,
                    SetupLow        => tsetup_A0_CLK,
                    HoldHigh        => thold_A0_CLK,
                    HoldLow         => thold_A0_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',