mt46v32m8.vhd

vhdl cod for ram.For sp3e

        w_5 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0);
        w_6 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1);
        w_7 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2);
        w_8 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3);
        w_9 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4);
        w_10 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5);
        w_11 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6);
        w_12 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7);
        w_21 : VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg);
        w_22 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_23 : VitalWireDelay (CKE_ipd, CKE, tipd_CKE);
        w_24 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_25 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_26 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_27 : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_28 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_29 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_30 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_31 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_32 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_33 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_34 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_35 : VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_36 : VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_47 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
        w_48 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg);
        w_49 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg);
        w_50 : VitalWireDelay (CASNeg_ipd, CASNeg, tipd_CASNeg);

    END BLOCK;

    WENeg_nwv <= To_UX01(WENeg_ipd);
    RASNeg_nwv <= To_UX01(RASNeg_ipd);
    CSNeg_nwv <= To_UX01(CSNeg_ipd);
    CASNeg_nwv <= To_UX01(CASNeg_ipd);
    CLKNeg_nwv <= To_UX01(CLKNeg_ipd);
    CLK_nwv <= To_UX01(CLK_ipd);
    CKE_nwv <= To_UX01(CKE_ipd);
    BA0_nwv <= To_UX01(BA0_ipd);
    BA1_nwv <= To_UX01(BA1_ipd);
    DM_nwv <= To_UX01(DM_ipd);
    DQS_nwv <= To_UX01(DQS_ipd);
    DQ0_nwv <= To_UX01(DQ0_ipd);
    DQ1_nwv <= To_UX01(DQ1_ipd);
    DQ2_nwv <= To_UX01(DQ2_ipd);
    DQ3_nwv <= To_UX01(DQ3_ipd);
    DQ4_nwv <= To_UX01(DQ4_ipd);
    DQ5_nwv <= To_UX01(DQ5_ipd);
    DQ6_nwv <= To_UX01(DQ6_ipd);
    DQ7_nwv <= To_UX01(DQ7_ipd);
    A0_nwv <= To_UX01(A0_ipd);
    A1_nwv <= To_UX01(A1_ipd);
    A2_nwv <= To_UX01(A2_ipd);
    A3_nwv <= To_UX01(A3_ipd);
    A4_nwv <= To_UX01(A4_ipd);
    A5_nwv <= To_UX01(A5_ipd);
    A6_nwv <= To_UX01(A6_ipd);
    A7_nwv <= To_UX01(A7_ipd);
    A8_nwv <= To_UX01(A8_ipd);
    A9_nwv <= To_UX01(A9_ipd);
    A10_nwv <= To_UX01(A10_ipd);
    A11_nwv <= To_UX01(A11_ipd);
    A12_nwv <= To_UX01(A12_ipd);

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Main : BLOCK

        PORT (
            BAIn            : IN    std_logic_vector(1 downto 0);
            DMIn            : IN    std_ulogic := 'U';
            DQSIn           : IN    std_ulogic := 'U';
            DataIn          : IN    std_logic_vector(HiDataBit downto 0);
            DataOut         : OUT   std_logic_vector(HiDataBit downto 0)
                                                     := (others => 'Z');
            DQSOut          : OUT   std_ulogic := 'Z';
            CLK_In          : IN    std_ulogic := 'Z';
            CLKNeg_In       : IN    std_ulogic := 'U';
            CKEIn           : IN    std_ulogic := 'U';
            AddressIn       : IN    std_logic_vector(HiAddrBit downto 0);
            WENegIn         : IN    std_ulogic := 'U';
            RASNegIn        : IN    std_ulogic := 'U';
            CSNegIn         : IN    std_ulogic := 'U';
            CASNegIn        : IN    std_ulogic := 'U'
        );
        PORT MAP (
            BAIn(0) => BA0_nwv,
            BAIn(1) => BA1_nwv,
            DMIn => DM_nwv,
            DQSIn => DQS_nwv,
            DQSOut => DQS,
            DataOut(0) =>  DQ0,
            DataOut(1) =>  DQ1,
            DataOut(2) =>  DQ2,
            DataOut(3) =>  DQ3,
            DataOut(4) =>  DQ4,
            DataOut(5) =>  DQ5,
            DataOut(6) =>  DQ6,
            DataOut(7) =>  DQ7,
            DataIn(0) =>  DQ0_nwv,
            DataIn(1) =>  DQ1_nwv,
            DataIn(2) =>  DQ2_nwv,
            DataIn(3) =>  DQ3_nwv,
            DataIn(4) =>  DQ4_nwv,
            DataIn(5) =>  DQ5_nwv,
            DataIn(6) =>  DQ6_nwv,
            DataIn(7) =>  DQ7_nwv,
            CLK_In => CLK_nwv,
            CLKNEG_In => CLKNeg_nwv,
            CKEIn => CKE_nwv,
            AddressIn(0) => A0_nwv,
            AddressIn(1) => A1_nwv,
            AddressIn(2) => A2_nwv,
            AddressIn(3) => A3_nwv,
            AddressIn(4) => A4_nwv,
            AddressIn(5) => A5_nwv,
            AddressIn(6) => A6_nwv,
            AddressIn(7) => A7_nwv,
            AddressIn(8) => A8_nwv,
            AddressIn(9) => A9_nwv,
            AddressIn(10) => A10_nwv,
            AddressIn(11) => A11_nwv,
            AddressIn(12) => A12_nwv,
            WENegIn => WENeg_nwv,
            RASNegIn => RASNeg_nwv,
            CSNegIn => CSNeg_nwv,
            CASNegIn => CASNeg_nwv
        );

        -- Type definition for state machine
        TYPE mem_state IS (pwron,
                           precharge,
                           idle,
                           mode_set,
                           self_refresh,
                           self_refresh_rec,
                           auto_refresh,
                           pwrdwn,
                           bank_act,
                           bank_act_pwrdwn,
                           write,
                           write_suspend,
                           read,
                           read_suspend,
                           write_auto_pre,
                           read_auto_pre,
                           write_sec,
                           read_sec
                          );

        TYPE statebanktype IS array (hi_bank downto 0) of mem_state;

        SIGNAL statebank : statebanktype;
        SIGNAL next_statebank : statebanktype;

        SIGNAL CAS_Lat  : NATURAL RANGE 2 to 3 := 2;
        SIGNAL D_zd     : std_logic_vector(HiDataBit DOWNTO 0);
        SIGNAL DQS_zd   : std_logic;
        SIGNAL DLL_EN   : boolean := false;
        SIGNAL DLL_reset: boolean := false;
        SIGNAL PERIOD   : time := 50 ns;       -- CLK period
        SIGNAL CLKint   : std_ulogic := '0';
        SIGNAL CLKtemp   : std_ulogic := '0';
        SIGNAL CLKcomb   : std_ulogic := '0';
        SIGNAL HalfPer   : Time := 0 ns;
        SIGNAL dlldelay  : Time := 0 ns;
        -----------------------------------------------------------------------
        SIGNAL clk_tmp1     : std_logic;
        SIGNAL clkneg_tmp1  : std_logic;
        SIGNAL clk_tmp2     : std_logic;
        SIGNAL clkneg_tmp2  : std_logic;

        SIGNAL CLKIn        : std_logic;
        SIGNAL CLKNegIn     : std_logic;

    BEGIN
    ---------------------------------------------------------------------------
    --delta cycle fix
    ---------------------------------------------------------------------------
    clk_tmp1    <= CLK_In ;
    clkneg_tmp1 <= CLKNeg_In;
    clk_tmp2    <= clk_tmp1;
    clkneg_tmp2 <= clkneg_tmp1;
    CLKIn       <= clk_tmp2;    --fixed
    CLKNegIn    <= clkneg_tmp2; --fixed
    ---------------------------------------------------------------------------

    PoweredUp <= true after tpowerup;
    CLKcomb <= CLKIn AND not(CLKNegIn);

    ----------------------------------------------
    -- DLL model functional section            ---
    ----------------------------------------------
    DLL: PROCESS(CLKcomb, CLKIn, CLKNegIn, CKSKWtrg)

        -- Timing Check Variables
        VARIABLE Sviol_CLK_CLKNeg    : X01 := '0';
        VARIABLE SD_CLK_CLKNeg       : VitalSkewDataType := VitalSkewDataInit;

        -- Functionality Results Variables
        VARIABLE Violation  : X01 := '0';

        VARIABLE Previous     : Time := 0 ns;
        VARIABLE TmpPer       : Time := 0 ns;

    BEGIN

        --------------------------------------------------------------------
        -- Timing Check Section
        --------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            VitalOutPhaseSkewCheck (
                Signal1         => CLKIn,
                Signal1Name     =>  "CLK",
                Signal2         => CLKNegIn,
                Signal2Name     =>  "CLKNeg",
                SkewS1S2RiseFall => tskew_CLK_CLKNeg,
                SkewS2S1RiseFall => tskew_CLK_CLKNeg,
                SkewS1S2FallRise => tskew_CLK_CLKNeg,
                SkewS2S1FallRise => tskew_CLK_CLKNeg,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & PartID,
                SkewData        => SD_CLK_CLKNeg,
                Trigger         => CKSKWtrg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Sviol_CLK_CLKNeg );

            Violation := Sviol_CLK_CLKNeg;

        END IF; -- Timing Check Section

    --------------------------------------------------------------------
    -- Functional Section
    --------------------------------------------------------------------

        IF rising_edge(CLKIn) AND  DLL_reset = TRUE THEN
            TmpPer := NOW - Previous;
            IF TmpPer > 0 ns THEN
                PERIOD <= TmpPer;
            END IF;
            Previous := NOW;
            HalfPer <= PERIOD/2;
            dlldelay <= PERIOD - tpd_CLK_DQ1;
        END IF;
	END PROCESS DLL;

    CLK_temp : PROCESS (CLKcomb)-- generating internal clock from DLL

    BEGIN
        IF DLL_reset = FALSE THEN
          CLKtemp <= TRANSPORT not(CLKtemp) AFTER HalfPer;
        END IF;
    END PROCESS;

	CLK_int : PROCESS (CLKcomb, CLKtemp)-- Passing clock based on DLL_EN

    BEGIN
        IF DLL_EN AND NOT DLL_reset then
            CLKint <= TRANSPORT CLKtemp AFTER dlldelay;
            CLKint <= CLKcomb;
        END IF;
    END PROCESS;

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
        Behavior : PROCESS (BAIn, DMIn, DQSIn, DataIn, CLKIn, CLKNegIn, CLKint,
                            CKEIn, AddressIn, WENegIn, RASNegIn, CSNegIn,
                            CASNegIn, PoweredUp)


            -- Type definition for commands
            TYPE command_type is (desl,
                                  nop,
                                  bst,
                                  read,
                                  writ,
                                  act,
                                  pre,
                                  mrs,
                                  ref
                                 );

            -- Timing Check Variables
            VARIABLE Tviol_BA_CLK       : X01 := '0';
            VARIABLE TD_BA_CLK          : VitalTimingDataType;

            VARIABLE Tviol_DM_CLK      : X01 := '0';
            VARIABLE TD_DM_CLK         : VitalTimingDataType;

            VARIABLE Tviol_D0_CLK       : X01 := '0';
            VARIABLE TD_D0_CLK          : VitalTimingDataType;