mt46v32m8.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: mt46v32m8.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2002, 2003 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:   | mod date: | changes made:
--    V1.0    B. Bizic     02 Sep 26   Initial release
--    V1.1    M.Marinkovic 02 Dec 15   Added DDL, changed output timing
--    V1.2    R. Munden    03 MAR 15   Changed type of some _nwv signals to
--                                     satisfy ncvhdl
--    V1.3    R. Munden    03 JUN 14   Removed DM valid check added CSNeg nop
--                                     Changed initialize values of some sigs
--                                     remove DM for reads, changed AR generic
--    V1.4    R. Munden    03 JUL 06   Fixed address problem in burst reads
--                                     Changed DQS to not drive 'X'
--                                     adjusted CL=2 timing
--    V1.5    R. Munden    03 AUG 09   Fixed timing problem with tRCD
--    V1.6    R. Munden    03 OCT 25   Enhaced memory preload capability
--    V1.7    M.Marinkovic 04 Jan 26   Fixed DQS Latch prior/at/after CLK edge
--                                     Fixed row/column address width problem
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    RAM
--  Technology: CMOS
--  Part:       MT46V32M8
--
--  Description: 8M x 8 x 4Banks Double Data Rate SDRAM
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE STD.textio.ALL;
                USE IEEE.VITAL_timing.all;
                USE IEEE.VITAL_primitives.all;

LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY mt46v32m8 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_BA0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQS                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DM                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CKE                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_RASNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CSNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_CASNeg              : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLK_DQ0              : VitalDelayType01Z := UnitDelay01Z;
        -- Access window / 2
        tpd_CLK_DQ1              : VitalDelayType    := UnitDelay;
        -- tpw values: pulse widths
        tpw_CLK_posedge          : VitalDelayType    := UnitDelay;
        tpw_CLK_negedge          : VitalDelayType    := UnitDelay;
        tpw_DQS_posedge          : VitalDelayType    := UnitDelay;
        -- tsetup values: setup times
        tsetup_A0_CLK           : VitalDelayType    := UnitDelay;
        tsetup_DQ0_CLK           : VitalDelayType    := UnitDelay;
        tsetup_DQS_CLK           : VitalDelayType    := UnitDelay;
        tsetup_DQ0_DQS           : VitalDelayType    := UnitDelay;
        tsetup_DM_DQS            : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        thold_A0_CLK             : VitalDelayType    := UnitDelay;
        thold_DQ0_CLK            : VitalDelayType    := UnitDelay;
        thold_DQS_CLK            : VitalDelayType    := UnitDelay;
        thold_DQ0_DQS            : VitalDelayType    := UnitDelay;
        thold_DM_DQS             : VitalDelayType    := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_CLK_posedge      : VitalDelayType    := UnitDelay;
        -- tskew values: skew times
        tskew_CLK_CLKNeg         : VitalDelayType    := UnitDelay;
        -- tdevice values: values for internal delays
        tdevice_REF              : VitalDelayType    := 15_625 ns;
        tdevice_TRC              : VitalDelayType    := 65 ns;
        tdevice_TRCD             : VitalDelayType    := 20 ns;
        tdevice_TRP              : VitalDelayType    := 20 ns;
        tdevice_TRFC             : VitalDelayType    := 70 ns;
        tdevice_TWR              : VitalDelayType    := 15 ns;
        tdevice_TRAS             : VitalDelayType01  := (40 ns, 120_000 ns);
        -- tpowerup: Power up initialization time. Data sheets say 200 us.
        -- May be shortened during simulation debug.
        tpowerup            : TIME      := 200 us;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        -- memory file to be loaded
        mem_file_name       : STRING    := "none";
                                        --"mt46v32m8.mem";
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        BA0             : IN    std_logic := 'U';
        BA1             : IN    std_logic := 'U';
        DM              : IN    std_logic := 'U';
        DQS             : INOUT std_logic := 'U';
        DQ0             : INOUT std_logic := 'U';
        DQ1             : INOUT std_logic := 'U';
        DQ2             : INOUT std_logic := 'U';
        DQ3             : INOUT std_logic := 'U';
        DQ4             : INOUT std_logic := 'U';
        DQ5             : INOUT std_logic := 'U';
        DQ6             : INOUT std_logic := 'U';
        DQ7             : INOUT std_logic := 'U';
        CLK             : IN    std_logic := 'U';
        CLKNeg          : IN    std_logic := 'U';
        CKE             : IN    std_logic := 'U';
        A0              : IN    std_logic := 'U';
        A1              : IN    std_logic := 'U';
        A2              : IN    std_logic := 'U';
        A3              : IN    std_logic := 'U';
        A4              : IN    std_logic := 'U';
        A5              : IN    std_logic := 'U';
        A6              : IN    std_logic := 'U';
        A7              : IN    std_logic := 'U';
        A8              : IN    std_logic := 'U';
        A9              : IN    std_logic := 'U';
        A10             : IN    std_logic := 'U';
        A11             : IN    std_logic := 'U';
        A12             : IN    std_logic := 'U';
        WENeg           : IN    std_logic := 'U';
        RASNeg          : IN    std_logic := 'U';
        CSNeg           : IN    std_logic := 'U';
        CASNeg          : IN    std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of mt46v32m8 : ENTITY IS TRUE;
END mt46v32m8;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of mt46v32m8 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "mt46v32m8";
    CONSTANT hi_bank        : NATURAL := 3;
    CONSTANT depth          : NATURAL := 8388607; --<< for simulation purpose
                                               -- real value is 8388607;
    CONSTANT HiAddrBit      : NATURAL := 12;
    CONSTANT HiColBit       : NATURAL := 9;
    CONSTANT HiDataBit      : NATURAL := 7;

    SIGNAL CKEreg              : X01 := 'X';
    SIGNAL PoweredUp           : boolean := false;

    SIGNAL BA0_ipd             : std_ulogic := 'U';
    SIGNAL BA1_ipd             : std_ulogic := 'U';
    SIGNAL DQS_ipd             : std_ulogic := 'U';
    SIGNAL DM_ipd              : std_ulogic := 'U';
    SIGNAL DQ0_ipd             : std_ulogic := 'U';
    SIGNAL DQ1_ipd             : std_ulogic := 'U';
    SIGNAL DQ2_ipd             : std_ulogic := 'U';
    SIGNAL DQ3_ipd             : std_ulogic := 'U';
    SIGNAL DQ4_ipd             : std_ulogic := 'U';
    SIGNAL DQ5_ipd             : std_ulogic := 'U';
    SIGNAL DQ6_ipd             : std_ulogic := 'U';
    SIGNAL DQ7_ipd             : std_ulogic := 'U';
    SIGNAL CLK_ipd             : std_ulogic := 'U';
    SIGNAL CLKNeg_ipd          : std_ulogic := 'U';
    SIGNAL CKE_ipd             : std_ulogic := 'U';
    SIGNAL A0_ipd              : std_ulogic := 'U';
    SIGNAL A1_ipd              : std_ulogic := 'U';
    SIGNAL A2_ipd              : std_ulogic := 'U';
    SIGNAL A3_ipd              : std_ulogic := 'U';
    SIGNAL A4_ipd              : std_ulogic := 'U';
    SIGNAL A5_ipd              : std_ulogic := 'U';
    SIGNAL A6_ipd              : std_ulogic := 'U';
    SIGNAL A7_ipd              : std_ulogic := 'U';
    SIGNAL A8_ipd              : std_ulogic := 'U';
    SIGNAL A9_ipd              : std_ulogic := 'U';
    SIGNAL A10_ipd             : std_ulogic := 'U';
    SIGNAL A11_ipd             : std_ulogic := 'U';
    SIGNAL A12_ipd             : std_ulogic := 'U';
    SIGNAL WENeg_ipd           : std_ulogic := 'U';
    SIGNAL RASNeg_ipd          : std_ulogic := 'U';
    SIGNAL CSNeg_ipd           : std_ulogic := 'U';
    SIGNAL CASNeg_ipd          : std_ulogic := 'U';

    SIGNAL BA0_nwv             : std_ulogic := 'U';
    SIGNAL BA1_nwv             : std_ulogic := 'U';
    SIGNAL DQS_nwv             : std_ulogic := 'U';
    SIGNAL DM_nwv              : std_ulogic := 'U';
    SIGNAL DQ0_nwv             : UX01 := 'U';
    SIGNAL DQ1_nwv             : UX01 := 'U';
    SIGNAL DQ2_nwv             : UX01 := 'U';
    SIGNAL DQ3_nwv             : UX01 := 'U';
    SIGNAL DQ4_nwv             : UX01 := 'U';
    SIGNAL DQ5_nwv             : UX01 := 'U';
    SIGNAL DQ6_nwv             : UX01 := 'U';
    SIGNAL DQ7_nwv             : UX01 := 'U';
    SIGNAL A0_nwv              : UX01 := 'U';
    SIGNAL A1_nwv              : UX01 := 'U';
    SIGNAL A2_nwv              : UX01 := 'U';
    SIGNAL A3_nwv              : UX01 := 'U';
    SIGNAL A4_nwv              : UX01 := 'U';
    SIGNAL A5_nwv              : UX01 := 'U';
    SIGNAL A6_nwv              : UX01 := 'U';
    SIGNAL A7_nwv              : UX01 := 'U';
    SIGNAL A8_nwv              : UX01 := 'U';
    SIGNAL A9_nwv              : UX01 := 'U';
    SIGNAL A10_nwv             : UX01 := 'U';
    SIGNAL A11_nwv             : UX01 := 'U';
    SIGNAL A12_nwv             : UX01 := 'U';
    SIGNAL CLK_nwv             : std_ulogic := 'U';
    SIGNAL CLKNeg_nwv          : std_ulogic := 'U';
    SIGNAL CKE_nwv             : std_ulogic := 'U';
    SIGNAL WENeg_nwv           : std_ulogic := 'U';
    SIGNAL RASNeg_nwv          : std_ulogic := 'U';
    SIGNAL CSNeg_nwv           : std_ulogic := 'U';
    SIGNAL CASNeg_nwv          : std_ulogic := 'U';

    SIGNAL CKSKWtrg          : std_ulogic := '0';
    SIGNAL rct_in            : std_ulogic := '0';
    SIGNAL rct_out           : std_ulogic := '0';
    SIGNAL rcdt_in           : std_ulogic_vector(3 downto 0) := (others => '0');
    SIGNAL rcdt_out          : std_ulogic_vector(3 downto 0) := (others => '0');
    SIGNAL pre_in            : std_ulogic := '0';
    SIGNAL pre_out           : std_ulogic := '0';
    SIGNAL refreshed_in      : std_ulogic := '0';
    SIGNAL refreshed_out     : std_ulogic := '0';
    SIGNAL rfc_out           : std_ulogic := '0';
    SIGNAL rfc_in            : std_ulogic := '0';
    SIGNAL wrt_in            : std_ulogic := '0';
    SIGNAL wrt_out           : std_ulogic := '0';
    SIGNAL ras_in            : std_ulogic_vector(3 downto 0) := (others => '0');
    SIGNAL ras_out           : std_ulogic_vector(3 downto 0) := (others => '0');

BEGIN

    ----------------------------------------------------------------------------
    -- Internal Delays
    ----------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays
    REF : VitalBuf (refreshed_out, refreshed_in, (UnitDelay, tdevice_REF));
    TRC : VitalBuf (rct_out, rct_in, (tdevice_TRC, VitalZeroDelay));
    TRCD : VitalBuf (rcdt_out(0), rcdt_in(0), (VitalZeroDelay, tdevice_TRCD));
    TRCD1 : VitalBuf (rcdt_out(1), rcdt_in(1), (VitalZeroDelay, tdevice_TRCD));
    TRCD2 : VitalBuf (rcdt_out(2), rcdt_in(2), (VitalZeroDelay, tdevice_TRCD));
    TRCD3 : VitalBuf (rcdt_out(3), rcdt_in(3), (VitalZeroDelay, tdevice_TRCD));
    TRP : VitalBuf (pre_out, pre_in, (tdevice_TRP, UnitDelay));
    TRFC  : VitalBuf (rfc_out, rfc_in, (tdevice_TRFC, UnitDelay));
    TWR : VitalBuf (wrt_out, wrt_in, (UnitDelay, tdevice_TWR));
    TRAS : VitalBuf (ras_out(0), ras_in(0), tdevice_TRAS);
    TRAS1 : VitalBuf (ras_out(1), ras_in(1), tdevice_TRAS);
    TRAS2 : VitalBuf (ras_out(2), ras_in(2), tdevice_TRAS);
    TRAS3 : VitalBuf (ras_out(3), ras_in(3), tdevice_TRAS);

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (BA0_ipd, BA0, tipd_BA0);
        w_2 : VitalWireDelay (BA1_ipd, BA1, tipd_BA1);
        w_3 : VitalWireDelay (DQS_ipd, DQS, tipd_DQS);
        w_4 : VitalWireDelay (DM_ipd, DM, tipd_DM);