idt703599.vhd

vhdl cod for ram.For sp3e

            VARIABLE TD_CE1RIn_CLKRIn          : VitalTimingDataType;

            VARIABLE Tviol_RWLIn_CLKLIn        : X01 := '0';
            VARIABLE TD_RWLIn_CLKLIn           : VitalTimingDataType;

            VARIABLE Tviol_RWRIn_CLKRIn        : X01 := '0';
            VARIABLE TD_RWRIn_CLKRIn           : VitalTimingDataType;

            VARIABLE Tviol_IOL3In_CLKLIn       : X01 := '0';
            VARIABLE TD_IOL3In_CLKLIn          : VitalTimingDataType;

            VARIABLE Tviol_IOL2In_CLKLIn       : X01 := '0';
            VARIABLE TD_IOL2In_CLKLIn          : VitalTimingDataType;

            VARIABLE Tviol_IOL1In_CLKLIn       : X01 := '0';
            VARIABLE TD_IOL1In_CLKLIn          : VitalTimingDataType;

            VARIABLE Tviol_IOL0In_CLKLIn       : X01 := '0';
            VARIABLE TD_IOL0In_CLKLIn          : VitalTimingDataType;

            VARIABLE Tviol_IOR3In_CLKRIn       : X01 := '0';
            VARIABLE TD_IOR3In_CLKRIn          : VitalTimingDataType;

            VARIABLE Tviol_IOR2In_CLKRIn       : X01 := '0';
            VARIABLE TD_IOR2In_CLKRIn          : VitalTimingDataType;

            VARIABLE Tviol_IOR1In_CLKRIn       : X01 := '0';
            VARIABLE TD_IOR1In_CLKRIn          : VitalTimingDataType;

            VARIABLE Tviol_IOR0In_CLKRIn       : X01 := '0';
            VARIABLE TD_IOR0In_CLKRIn          : VitalTimingDataType;

            VARIABLE Tviol_BE3RNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_BE3RNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_BE2RNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_BE2RNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_BE1RNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_BE1RNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_BE0RNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_BE0RNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_BE3LNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_BE3LNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_BE2LNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_BE2LNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_BE1LNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_BE1LNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_BE0LNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_BE0LNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_ADSLNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_ADSLNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_ADSRNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_ADSRNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_CNTENLNegIn_CLKLIn  :  X01 := '0';
            VARIABLE TD_CNTENLNegIn_CLKLIn     : VitalTimingDataType;

            VARIABLE Tviol_CNTENRNegIn_CLKRIn  :  X01 := '0';
            VARIABLE TD_CNTENRNegIn_CLKRIn     : VitalTimingDataType;

            VARIABLE Tviol_REPEATLNegIn_CLKLIn :  X01 := '0';
            VARIABLE TD_REPEATLNegIn_CLKLIn    : VitalTimingDataType;

            VARIABLE Tviol_REPEATRNegIn_CLKRIn :  X01 := '0';
            VARIABLE TD_REPEATRNegIn_CLKRIn    : VitalTimingDataType;

            VARIABLE Pviol_CLKLIn0             :  X01 := '0';
            VARIABLE TD_CLKLIn0    : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_CLKRIn0             :  X01 := '0';
            VARIABLE TD_CLKRIn0    : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_CLKLIn1             :  X01 := '0';
            VARIABLE TD_CLKLIn1    : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_CLKRIn1             :  X01 := '0';
            VARIABLE TD_CLKRIn1    : VitalPeriodDataType := VitalPeriodDataInit;

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
                             RANGE  -2 TO MaxData;

            VARIABLE DataL3Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataL2Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataL1Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataL0Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataR3Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataR2Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataR1Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataR0Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE JTAGL3Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE JTAGL2Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE JTAGL1Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE JTAGL0Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE JTAGR3Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE JTAGR2Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE JTAGR1Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE JTAGR0Drive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataL3tmp   : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataL2tmp   : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataL1tmp   : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataL0tmp   : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataR3tmp   : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataR2tmp   : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataR1tmp   : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataR0tmp   : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataTempL3  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE DataTempL2  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE DataTempL1  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE DataTempL0  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE DataTempR3  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE DataTempR2  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE DataTempR1  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE DataTempR0  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE WrtDataL3   : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE WrtDataL2   : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE WrtDataL1   : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE WrtDataL0   : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE WrtDataR3   : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE WrtDataR2   : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE WrtDataR1   : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE WrtDataR0   : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE LocationL  : NATURAL RANGE 0 TO TotalLOC := 0;
            VARIABLE LocationR  : NATURAL RANGE 0 TO TotalLOC := 0;
            VARIABLE LastLocL   : NATURAL RANGE 0 TO TotalLOC := 0;
            VARIABLE LastLocR   : NATURAL RANGE 0 TO TotalLOC := 0;
            VARIABLE MemData3   : MemStore;
            VARIABLE MemData2   : MemStore;
            VARIABLE MemData1   : MemStore;
            VARIABLE MemData0   : MemStore;
            VARIABLE LatencyL   : BOOLEAN;
            VARIABLE LatencyR   : BOOLEAN;

            -- No Weak Values Variables
            VARIABLE CE0LNeg_nwv       : UX01 := 'U';
            VARIABLE CE0RNeg_nwv       : UX01 := 'U';
            VARIABLE CE1L_nwv          : UX01 := 'U';
            VARIABLE CE1R_nwv          : UX01 := 'U';
            VARIABLE CE0LNeg_reg       : UX01 := 'U';
            VARIABLE CE0RNeg_reg       : UX01 := 'U';
            VARIABLE CE1L_reg          : UX01 := 'U';
            VARIABLE CE1R_reg          : UX01 := 'U';
            VARIABLE RWR_nwv           : UX01 := 'U';
            VARIABLE RWL_nwv           : UX01 := 'U';
            VARIABLE ADSLNeg_nwv       : UX01 := 'U';
            VARIABLE ADSRNeg_nwv       : UX01 := 'U';
            VARIABLE OELNeg_nwv        : UX01 := 'U';
            VARIABLE OERNeg_nwv        : UX01 := 'U';
            VARIABLE BE3LNeg_nwv       : UX01 := 'U';
            VARIABLE BE2LNeg_nwv       : UX01 := 'U';
            VARIABLE BE1LNeg_nwv       : UX01 := 'U';
            VARIABLE BE0LNeg_nwv       : UX01 := 'U';
            VARIABLE BE3RNeg_nwv       : UX01 := 'U';
            VARIABLE BE2RNeg_nwv       : UX01 := 'U';
            VARIABLE BE1RNeg_nwv       : UX01 := 'U';
            VARIABLE BE0RNeg_nwv       : UX01 := 'U';
            VARIABLE BE3LNeg_reg       : UX01 := 'U';
            VARIABLE BE2LNeg_reg       : UX01 := 'U';
            VARIABLE BE1LNeg_reg       : UX01 := 'U';
            VARIABLE BE0LNeg_reg       : UX01 := 'U';
            VARIABLE BE3RNeg_reg       : UX01 := 'U';
            VARIABLE BE2RNeg_reg       : UX01 := 'U';
            VARIABLE BE1RNeg_reg       : UX01 := 'U';
            VARIABLE BE0RNeg_reg       : UX01 := 'U';
            VARIABLE REPEATLNeg_nwv    : UX01 := 'U';
            VARIABLE REPEATRNeg_nwv    : UX01 := 'U';
            VARIABLE CNTENLNeg_nwv     : UX01 := 'U';
            VARIABLE CNTENRNeg_nwv     : UX01 := 'U';

        BEGIN
            CE0LNeg_nwv    := To_UX01 (s => CE0LNegIn);
            CE0RNeg_nwv    := To_UX01 (s => CE0RNegIn);
            CE1L_nwv       := To_UX01 (s => CE1LIn);
            CE1R_nwv       := To_UX01 (s => CE1RIn);
            RWL_nwv        := To_UX01 (s => RWLIn);
            RWR_nwv        := To_UX01 (s => RWRIn);
            ADSLNeg_nwv    := To_UX01 (s => ADSLNegIn);
            ADSRNeg_nwv    := To_UX01 (s => ADSRNegIn);
            OELNeg_nwv     := To_UX01 (s => OELNegIn);
            OERNeg_nwv     := To_UX01 (s => OERNegIn);
            BE3LNeg_nwv    := To_UX01 (s => BE3LNegIn);
            BE2LNeg_nwv    := To_UX01 (s => BE2LNegIn);
            BE1LNeg_nwv    := To_UX01 (s => BE1LNegIn);
            BE0LNeg_nwv    := To_UX01 (s => BE0LNegIn);
            BE3RNeg_nwv    := To_UX01 (s => BE3RNegIn);
            BE2RNeg_nwv    := To_UX01 (s => BE2RNegIn);
            BE1RNeg_nwv    := To_UX01 (s => BE1RNegIn);
            BE0RNeg_nwv    := To_UX01 (s => BE0RNegIn);
            REPEATLNeg_nwv := To_UX01 (s => REPEATLNegIn);
            REPEATRNeg_nwv := To_UX01 (s => REPEATRNegIn);
            CNTENLNeg_nwv  := To_UX01 (s => CNTENLNegIn);
            CNTENRNeg_nwv  := To_UX01 (s => CNTENRNegIn);

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => ALIn,
                    TestSignalName  => "AL",
                    RefSignal       => CLKLIn,
                    RefSignalName   => "CLKL",
                    SetupHigh       => tsetup_AL0_CLKL,
                    SetupLow        => tsetup_AL0_CLKL,
                    HoldHigh        => thold_AL0_CLKL,
                    HoldLow         => thold_AL0_CLKL,
                    CheckEnabled    => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ALIn_CLKLIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ALIn_CLKLIn );

                VitalSetupHoldCheck (
                    TestSignal      => ARIn,
                    TestSignalName  => "AR",
                    RefSignal       => CLK