idt703599.vhd

vhdl cod for ram.For sp3e

    SIGNAL IOL10_ipd           : std_ulogic := 'U';
    SIGNAL IOL9_ipd            : std_ulogic := 'U';
    SIGNAL IOL8_ipd            : std_ulogic := 'U';
    SIGNAL IOL7_ipd            : std_ulogic := 'U';
    SIGNAL IOL6_ipd            : std_ulogic := 'U';
    SIGNAL IOL5_ipd            : std_ulogic := 'U';
    SIGNAL IOL4_ipd            : std_ulogic := 'U';
    SIGNAL IOL3_ipd            : std_ulogic := 'U';
    SIGNAL IOL2_ipd            : std_ulogic := 'U';
    SIGNAL IOL1_ipd            : std_ulogic := 'U';
    SIGNAL IOL0_ipd            : std_ulogic := 'U';
    SIGNAL AR0_ipd             : std_ulogic := 'U';
    SIGNAL AR1_ipd             : std_ulogic := 'U';
    SIGNAL AR2_ipd             : std_ulogic := 'U';
    SIGNAL AR3_ipd             : std_ulogic := 'U';
    SIGNAL AR4_ipd             : std_ulogic := 'U';
    SIGNAL AR5_ipd             : std_ulogic := 'U';
    SIGNAL AR6_ipd             : std_ulogic := 'U';
    SIGNAL AR7_ipd             : std_ulogic := 'U';
    SIGNAL AR8_ipd             : std_ulogic := 'U';
    SIGNAL AR9_ipd             : std_ulogic := 'U';
    SIGNAL AR10_ipd            : std_ulogic := 'U';
    SIGNAL AR11_ipd            : std_ulogic := 'U';
    SIGNAL AR12_ipd            : std_ulogic := 'U';
    SIGNAL AR13_ipd            : std_ulogic := 'U';
    SIGNAL AR14_ipd            : std_ulogic := 'U';
    SIGNAL AR15_ipd            : std_ulogic := 'U';
    SIGNAL AR16_ipd            : std_ulogic := 'U';
    SIGNAL AL0_ipd             : std_ulogic := 'U';
    SIGNAL AL1_ipd             : std_ulogic := 'U';
    SIGNAL AL2_ipd             : std_ulogic := 'U';
    SIGNAL AL3_ipd             : std_ulogic := 'U';
    SIGNAL AL4_ipd             : std_ulogic := 'U';
    SIGNAL AL5_ipd             : std_ulogic := 'U';
    SIGNAL AL6_ipd             : std_ulogic := 'U';
    SIGNAL AL7_ipd             : std_ulogic := 'U';
    SIGNAL AL8_ipd             : std_ulogic := 'U';
    SIGNAL AL9_ipd             : std_ulogic := 'U';
    SIGNAL AL10_ipd            : std_ulogic := 'U';
    SIGNAL AL11_ipd            : std_ulogic := 'U';
    SIGNAL AL12_ipd            : std_ulogic := 'U';
    SIGNAL AL13_ipd            : std_ulogic := 'U';
    SIGNAL AL14_ipd            : std_ulogic := 'U';
    SIGNAL AL15_ipd            : std_ulogic := 'U';
    SIGNAL AL16_ipd            : std_ulogic := 'U';
    SIGNAL TDI_ipd             : std_ulogic := 'U';
    SIGNAL TCK_ipd             : std_ulogic := 'U';
    SIGNAL TMS_ipd             : std_ulogic := 'U';
    SIGNAL TRSTNeg_ipd         : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (RWR_ipd, RWR, tipd_RWR);
        w_2 : VitalWireDelay (RWL_ipd, RWL, tipd_RWL);
        w_3 : VitalWireDelay (CE1R_ipd, CE1R, tipd_CE1R);
        w_4 : VitalWireDelay (CE1L_ipd, CE1L, tipd_CE1L);
        w_5 : VitalWireDelay (PIPER_ipd, PIPER, tipd_PIPER);
        w_6 : VitalWireDelay (PIPEL_ipd, PIPEL, tipd_PIPEL);
        w_7 : VitalWireDelay (CLKR_ipd, CLKR, tipd_CLKR);
        w_8 : VitalWireDelay (CLKL_ipd, CLKL, tipd_CLKL);
        w_9 : VitalWireDelay (CNTENRNeg_ipd, CNTENRNeg, tipd_CNTENRNeg);
        w_10 : VitalWireDelay (CNTENLNeg_ipd, CNTENLNeg, tipd_CNTENLNeg);
        w_11 : VitalWireDelay (REPEATRNeg_ipd, REPEATRNeg, tipd_REPEATRNeg);
        w_12 : VitalWireDelay (REPEATLNeg_ipd, REPEATLNeg, tipd_REPEATLNeg);
        w_13 : VitalWireDelay (ADSRNeg_ipd, ADSRNeg, tipd_ADSRNeg);
        w_14 : VitalWireDelay (ADSLNeg_ipd, ADSLNeg, tipd_ADSLNeg);
        w_15 : VitalWireDelay (CE0RNeg_ipd, CE0RNeg, tipd_CE0RNeg);
        w_16 : VitalWireDelay (CE0LNeg_ipd, CE0LNeg, tipd_CE0LNeg);
        w_17 : VitalWireDelay (OERNeg_ipd, OERNeg, tipd_OERNeg);
        w_18 : VitalWireDelay (OELNeg_ipd, OELNeg, tipd_OELNeg);
        w_19a : VitalWireDelay (BE3RNeg_ipd, BE3RNeg, tipd_BE3RNeg);
        w_19b : VitalWireDelay (BE2RNeg_ipd, BE2RNeg, tipd_BE2RNeg);
        w_19 : VitalWireDelay (BE1RNeg_ipd, BE1RNeg, tipd_BE1RNeg);
        w_20 : VitalWireDelay (BE0RNeg_ipd, BE0RNeg, tipd_BE0RNeg);
        w_21a : VitalWireDelay (BE3LNeg_ipd, BE3LNeg, tipd_BE3LNeg);
        w_21b : VitalWireDelay (BE2LNeg_ipd, BE2LNeg, tipd_BE2LNeg);
        w_21 : VitalWireDelay (BE1LNeg_ipd, BE1LNeg, tipd_BE1LNeg);
        w_22 : VitalWireDelay (BE0LNeg_ipd, BE0LNeg, tipd_BE0LNeg);
        w_23 : VitalWireDelay (AR0_ipd, AR0, tipd_AR0);
        w_24 : VitalWireDelay (AR1_ipd, AR1, tipd_AR1);
        w_25 : VitalWireDelay (AR2_ipd, AR2, tipd_AR2);
        w_26 : VitalWireDelay (AR3_ipd, AR3, tipd_AR3);
        w_27 : VitalWireDelay (AR4_ipd, AR4, tipd_AR4);
        w_28 : VitalWireDelay (AR5_ipd, AR5, tipd_AR5);
        w_29 : VitalWireDelay (AR6_ipd, AR6, tipd_AR6);
        w_30 : VitalWireDelay (AR7_ipd, AR7, tipd_AR7);
        w_31 : VitalWireDelay (AR8_ipd, AR8, tipd_AR8);
        w_32 : VitalWireDelay (AR9_ipd, AR9, tipd_AR9);
        w_33 : VitalWireDelay (AR10_ipd, AR10, tipd_AR10);
        w_34 : VitalWireDelay (AR11_ipd, AR11, tipd_AR11);
        w_35 : VitalWireDelay (AR12_ipd, AR12, tipd_AR12);
        w_36 : VitalWireDelay (AR13_ipd, AR13, tipd_AR13);
        w_37 : VitalWireDelay (AR14_ipd, AR14, tipd_AR14);
        w_38 : VitalWireDelay (AR15_ipd, AR15, tipd_AR15);
        w_39 : VitalWireDelay (AR16_ipd, AR16, tipd_AR16);
        w_41 : VitalWireDelay (AL0_ipd, AL0, tipd_AL0);
        w_42 : VitalWireDelay (AL1_ipd, AL1, tipd_AL1);
        w_43 : VitalWireDelay (AL2_ipd, AL2, tipd_AL2);
        w_44 : VitalWireDelay (AL3_ipd, AL3, tipd_AL3);
        w_45 : VitalWireDelay (AL4_ipd, AL4, tipd_AL4);
        w_46 : VitalWireDelay (AL5_ipd, AL5, tipd_AL5);
        w_47 : VitalWireDelay (AL6_ipd, AL6, tipd_AL6);
        w_48 : VitalWireDelay (AL7_ipd, AL7, tipd_AL7);
        w_49 : VitalWireDelay (AL8_ipd, AL8, tipd_AL8);
        w_50 : VitalWireDelay (AL9_ipd, AL9, tipd_AL9);
        w_51 : VitalWireDelay (AL10_ipd, AL10, tipd_AL10);
        w_52 : VitalWireDelay (AL11_ipd, AL11, tipd_AL11);
        w_53 : VitalWireDelay (AL12_ipd, AL12, tipd_AL12);
        w_54 : VitalWireDelay (AL13_ipd, AL13, tipd_AL13);
        w_55 : VitalWireDelay (AL14_ipd, AL14, tipd_AL14);
        w_56 : VitalWireDelay (AL15_ipd, AL15, tipd_AL15);
        w_57 : VitalWireDelay (AL16_ipd, AL16, tipd_AL16);
        w_58 : VitalWireDelay (IOR35_ipd, IOR35, tipd_IOR35);
        w_59 : VitalWireDelay (IOR34_ipd, IOR34, tipd_IOR34);
        w_60 : VitalWireDelay (IOR33_ipd, IOR33, tipd_IOR33);
        w_61 : VitalWireDelay (IOR32_ipd, IOR32, tipd_IOR32);
        w_62 : VitalWireDelay (IOR31_ipd, IOR31, tipd_IOR31);
        w_63 : VitalWireDelay (IOR30_ipd, IOR30, tipd_IOR30);
        w_64 : VitalWireDelay (IOR29_ipd, IOR29, tipd_IOR29);
        w_65 : VitalWireDelay (IOR28_ipd, IOR28, tipd_IOR28);
        w_66 : VitalWireDelay (IOR27_ipd, IOR27, tipd_IOR27);
        w_67 : VitalWireDelay (IOR26_ipd, IOR26, tipd_IOR26);
        w_68 : VitalWireDelay (IOR25_ipd, IOR25, tipd_IOR25);
        w_69 : VitalWireDelay (IOR24_ipd, IOR24, tipd_IOR24);
        w_70 : VitalWireDelay (IOR23_ipd, IOR23, tipd_IOR23);
        w_71 : VitalWireDelay (IOR22_ipd, IOR22, tipd_IOR22);
        w_72 : VitalWireDelay (IOR21_ipd, IOR21, tipd_IOR21);
        w_73 : VitalWireDelay (IOR20_ipd, IOR20, tipd_IOR20);
        w_74 : VitalWireDelay (IOR19_ipd, IOR19, tipd_IOR19);
        w_75 : VitalWireDelay (IOR18_ipd, IOR18, tipd_IOR18);
        w_76 : VitalWireDelay (IOR17_ipd, IOR17, tipd_IOR17);
        w_77 : VitalWireDelay (IOR16_ipd, IOR16, tipd_IOR16);
        w_78 : VitalWireDelay (IOR15_ipd, IOR15, tipd_IOR15);
        w_79 : VitalWireDelay (IOR14_ipd, IOR14, tipd_IOR14);
        w_80 : VitalWireDelay (IOR13_ipd, IOR13, tipd_IOR13);
        w_81 : VitalWireDelay (IOR12_ipd, IOR12, tipd_IOR12);
        w_82 : VitalWireDelay (IOR11_ipd, IOR11, tipd_IOR11);
        w_83 : VitalWireDelay (IOR10_ipd, IOR10, tipd_IOR10);
        w_84 : VitalWireDelay (IOR9_ipd, IOR9, tipd_IOR9);
        w_85 : VitalWireDelay (IOR8_ipd, IOR8, tipd_IOR8);
        w_86 : VitalWireDelay (IOR7_ipd, IOR7, tipd_IOR7);
        w_87 : VitalWireDelay (IOR6_ipd, IOR6, tipd_IOR6);
        w_88 : VitalWireDelay (IOR5_ipd, IOR5, tipd_IOR5);
        w_89 : VitalWireDelay (IOR4_ipd, IOR4, tipd_IOR4);
        w_90 : VitalWireDelay (IOR3_ipd, IOR3, tipd_IOR3);
        w_91 : VitalWireDelay (IOR2_ipd, IOR2, tipd_IOR2);
        w_92 : VitalWireDelay (IOR1_ipd, IOR1, tipd_IOR1);
        w_93 : VitalWireDelay (IOR0_ipd, IOR0, tipd_IOR0);
        w_94 : VitalWireDelay (IOL35_ipd, IOL35, tipd_IOL35);
        w_95 : VitalWireDelay (IOL34_ipd, IOL34, tipd_IOL34);
        w_96 : VitalWireDelay (IOL33_ipd, IOL33, tipd_IOL33);
        w_97 : VitalWireDelay (IOL32_ipd, IOL32, tipd_IOL32);
        w_98 : VitalWireDelay (IOL31_ipd, IOL31, tipd_IOL31);
        w_99 : VitalWireDelay (IOL30_ipd, IOL30, tipd_IOL30);
        w_101 : VitalWireDelay (IOL29_ipd, IOL29, tipd_IOL29);
        w_102 : VitalWireDelay (IOL28_ipd, IOL28, tipd_IOL28);
        w_103 : VitalWireDelay (IOL27_ipd, IOL27, tipd_IOL27);
        w_104 : VitalWireDelay (IOL26_ipd, IOL26, tipd_IOL26);
        w_105 : VitalWireDelay (IOL25_ipd, IOL25, tipd_IOL25);
        w_106 : VitalWireDelay (IOL24_ipd, IOL24, tipd_IOL24);
        w_107 : VitalWireDelay (IOL23_ipd, IOL23, tipd_IOL23);
        w_108 : VitalWireDelay (IOL22_ipd, IOL22, tipd_IOL22);
        w_109 : VitalWireDelay (IOL21_ipd, IOL21, tipd_IOL21);
        w_110 : VitalWireDelay (IOL20_ipd, IOL20, tipd_IOL20);
        w_111 : VitalWireDelay (IOL19_ipd, IOL19, tipd_IOL19);
        w_112 : VitalWireDelay (IOL18_ipd, IOL18, tipd_IOL18);
        w_113 : VitalWireDelay (IOL17_ipd, IOL17, tipd_IOL17);
        w_114 : VitalWireDelay (IOL16_ipd, IOL16, tipd_IOL16);
        w_115 : VitalWireDelay (IOL15_ipd, IOL15, tipd_IOL15);
        w_116 : VitalWireDelay (IOL14_ipd, IOL14, tipd_IOL14);
        w_117 : VitalWireDelay (IOL13_ipd, IOL13, tipd_IOL13);
        w_118 : VitalWireDelay (IOL12_ipd, IOL12, tipd_IOL12);
        w_119 : VitalWireDelay (IOL11_ipd, IOL11, tipd_IOL11);
        w_120 : VitalWireDelay (IOL10_ipd, IOL10, tipd_IOL10);
        w_121 : VitalWireDelay (IOL9_ipd, IOL9, tipd_IOL9);
        w_122 : VitalWireDelay (IOL8_ipd, IOL8, tipd_IOL8);
        w_123 : VitalWireDelay (IOL7_ipd, IOL7, tipd_IOL7);
        w_124 : VitalWireDelay (IOL6_ipd, IOL6, tipd_IOL6);
        w_125 : VitalWireDelay (IOL5_ipd, IOL5, tipd_IOL5);
        w_126 : VitalWireDelay (IOL4_ipd, IOL4, tipd_IOL4);
        w_127 : VitalWireDelay (IOL3_ipd, IOL3, tipd_IOL3);
        w_128 : VitalWireDelay (IOL2_ipd, IOL2, tipd_IOL2);
        w_129 : VitalWireDelay (IOL1_ipd, IOL1, tipd_IOL1);
        w_130 : VitalWireDelay (IOL0_ipd, IOL0, tipd_IOL0);
        w_131 : VitalWireDelay (TDI_ipd, TDI, tipd_TDI);
        w_132 : VitalWireDelay (TCK_ipd, TCK, tipd_TCK);
        w_133 : VitalWireDelay (TMS_ipd, TMS, tipd_TMS);
        w_134 : VitalWireDelay (TRSTNeg_ipd, TRSTNeg, tipd_TRSTNeg);
        w_135 : VitalWireDelay (OPTR_ipd, OPTR, tipd_OPTR);
        w_136 : VitalWireDelay (OPTL_ipd, OPTL, tipd_OPTL);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            ALIn         : IN    std_logic_vector(HiAbit downto 0);
            ARIn         : IN    std_logic_vector(HiAbit downto 0);
            IOL3In       : IN    std_logic_vector(HiDbit downto 0);
            IOR3In       : IN    std_logic_vector(HiDbit downto 0);
            IOL2In       : IN    std_logic_vector(HiDbit downto 0);
            IOR2In       : IN    std_logic_vector(HiDbit downto 0);
            IOL1In       : IN    std_logic_vector(HiDbit downto 0);
            IOR1In       : IN    std_logic_vector(HiDbit downto 0);
            IOL0In       : IN    std_logic_vector(HiDbit downto 0);
            IOR0In       : IN    std_logic_vector(HiDbit downto 0);
            IOL3Out      : OUT   std_logic_vector(HiDbit downto 0);
            IOR3Out      : OUT   std_logic_vector(HiDbit downto 0);
            IOL2Out      : OUT   std_logic_vector(HiDbit downto 0);
            IOR2Out      : OUT   std_logic_vector(HiDbit downto 0);
            IOL1Out      : OUT   std_logic_vector(HiDbit downto 0);
            IOR1Out      : OUT   std_logic_vector(HiDbit downto 0);
            IOL0Out      : OUT   std_logic_vector(HiDbit downto 0);
            IOR0Out      : OUT   std_logic_vector(HiDbit downto 0);
            OPTRIn       : IN    std_ulogic := 'U';
            OPTLIn       : IN    std_ulogic := 'U';
            RWLIn        : IN    std_ulogic := 'U';
            RWRIn        : IN    std_ulogic := 'U';
            OELNegIn     : IN    std_ulogic := 'U';
            OERNegIn     : IN    std_ulogic := 'U';
            BE3LNegIn    : IN    std_ulogic := 'U';
            BE2LNegIn    : IN    std_ulogic := 'U';
            BE1LNegIn    : IN    std_ulogic := 'U';
            BE0LNegIn    : IN    std_ulogic := 'U';
            BE3RNegIn    : IN    std_ulogic := 'U';
            BE2RNegIn    : IN    std_ulogic := 'U';
            BE1RNegIn    : IN    std_ulogic := 'U';
            BE0RNegIn    : IN    std_ulogic := 'U';
            CE0LNegIn    : IN    std_ulogic := 'U';
            CE0RNegIn    : IN    std_ulogic := 'U';
            CE1LIn       : IN    std_ulogic := 'U';
            CE1RIn       : IN    std_ulogic := 'U';
            CLKLIn       : IN    std_ulogic := 'U';
            CLKRIn       : IN    std_ulogic := 'U';
            REPEATLNegIn : IN    std_ulogic := 'U';
            REPEATRNegIn : IN    std_ulogic := 'U';
            CNTENRNegIn  : IN    std_ulogic := 'U';
            CNTENLNegIn  : IN    std_ulogic := 'U';
            ADSRNegIn    : IN    std_ulogic := 'U';
            ADSLNegIn    : IN    std_ulogic := 'U';
            PIPERIn      : IN    std_ulogic := '1';
            PIPELIn      : IN    std_ulogic := '1';
            TDIIn        : IN    std_ulogic := '1';
            TCKIn        : IN    std_ulogic := '1';
            TMSIn        : IN    std_ulogic := '1';
            TRSTNegIn    : IN    std_ulogic := '1'
        );
        PORT MAP (