📄 idt703599.vhd
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---------------------------------------------------------------------------------- File Name: idt703599.vhd---------------------------------------------------------------------------------- Copyright (C) 2001 Integrated Device Technology; http://www.idt.com/-- Developed & supported by Free Model Foundry; http://www.FreeModelFoundry.com---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no-- warranty with respect to the information contained herein. IDT DISCLAIMS-- AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE-- ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN-- NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN-- CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL,-- CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR-- APPLICATION OF THE VHDL model. Further, IDT reserves the right to make-- changes without notice to any product herein to improve reliability,-- function, or design. IDT does not convey any license under patent rights-- or any other intellectual property rights, including those of third parties.-- IDT is not obligated to provide maintenance or support for the licensed VHDL-- model.---- MODIFICATION HISTORY:---- version: | author: | mod date: | changes made:-- V1.0 R. Munden 01 Mar 22 Initial release-- V1.1 R. Munden 01 Nov 10 Corrected address cntr w/o enable------------------------------------------------------------------------------------ PART DESCRIPTION:---- Library: RAM-- Technology: CMOS-- Part: IDT703599---- Description: Sync Pipelined Dual-Port SRAM 128K x 36--------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL;LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY idt703599 IS GENERIC ( -- tipd delays: interconnect path delays tipd_OPTR : VitalDelayType01 := VitalZeroDelay01; tipd_OPTL : VitalDelayType01 := VitalZeroDelay01; tipd_RWR : VitalDelayType01 := VitalZeroDelay01; tipd_RWL : VitalDelayType01 := VitalZeroDelay01; tipd_CE1R : VitalDelayType01 := VitalZeroDelay01; tipd_CE1L : VitalDelayType01 := VitalZeroDelay01; tipd_PIPER : VitalDelayType01 := VitalZeroDelay01; tipd_PIPEL : VitalDelayType01 := VitalZeroDelay01; tipd_CLKR : VitalDelayType01 := VitalZeroDelay01; tipd_CLKL : VitalDelayType01 := VitalZeroDelay01; tipd_CNTENRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTENLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_REPEATRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_REPEATLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ADSRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ADSLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OERNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OELNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE3RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE2RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE1RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE0RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE3LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE2LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE1LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE0LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_IOR35 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR34 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR33 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR32 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR31 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR30 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR29 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR28 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR27 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR26 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR25 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR24 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR23 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR22 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR21 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR20 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR19 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR18 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR17 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR16 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR15 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR14 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR13 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR12 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR11 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR10 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR9 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR8 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR0 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL35 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL34 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL33 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL32 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL31 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL30 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL29 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL28 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL27 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL26 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL25 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL24 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL23 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL22 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL21 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL20 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL19 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL18 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL17 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL16 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL15 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL14 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL13 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL12 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL11 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL10 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL9 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL8 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL0 : VitalDelayType01 := VitalZeroDelay01; tipd_AR0 : VitalDelayType01 := VitalZeroDelay01; tipd_AR1 : VitalDelayType01 := VitalZeroDelay01; tipd_AR2 : VitalDelayType01 := VitalZeroDelay01; tipd_AR3 : VitalDelayType01 := VitalZeroDelay01; tipd_AR4 : VitalDelayType01 := VitalZeroDelay01; tipd_AR5 : VitalDelayType01 := VitalZeroDelay01; tipd_AR6 : VitalDelayType01 := VitalZeroDelay01; tipd_AR7 : VitalDelayType01 := VitalZeroDelay01; tipd_AR8 : VitalDelayType01 := VitalZeroDelay01; tipd_AR9 : VitalDelayType01 := VitalZeroDelay01; tipd_AR10 : VitalDelayType01 := VitalZeroDelay01; tipd_AR11 : VitalDelayType01 := VitalZeroDelay01; tipd_AR12 : VitalDelayType01 := VitalZeroDelay01; tipd_AR13 : VitalDelayType01 := VitalZeroDelay01; tipd_AR14 : VitalDelayType01 := VitalZeroDelay01; tipd_AR15 : VitalDelayType01 := VitalZeroDelay01; tipd_AR16 : VitalDelayType01 := VitalZeroDelay01; tipd_AL0 : VitalDelayType01 := VitalZeroDelay01; tipd_AL1 : VitalDelayType01 := VitalZeroDelay01; tipd_AL2 : VitalDelayType01 := VitalZeroDelay01; tipd_AL3 : VitalDelayType01 := VitalZeroDelay01; tipd_AL4 : VitalDelayType01 := VitalZeroDelay01; tipd_AL5 : VitalDelayType01 := VitalZeroDelay01; tipd_AL6 : VitalDelayType01 := VitalZeroDelay01; tipd_AL7 : VitalDelayType01 := VitalZeroDelay01; tipd_AL8 : VitalDelayType01 := VitalZeroDelay01; tipd_AL9 : VitalDelayType01 := VitalZeroDelay01; tipd_AL10 : VitalDelayType01 := VitalZeroDelay01; tipd_AL11 : VitalDelayType01 := VitalZeroDelay01; tipd_AL12 : VitalDelayType01 := VitalZeroDelay01; tipd_AL13 : VitalDelayType01 := VitalZeroDelay01; tipd_AL14 : VitalDelayType01 := VitalZeroDelay01; tipd_AL15 : VitalDelayType01 := VitalZeroDelay01; tipd_AL16 : VitalDelayType01 := VitalZeroDelay01; tipd_TDI : VitalDelayType01 := VitalZeroDelay01; tipd_TCK : VitalDelayType01 := VitalZeroDelay01; tipd_TMS : VitalDelayType01 := VitalZeroDelay01; tipd_TRSTNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays -- tOE, tOLZ, tOHZ tpd_OELNeg_IOL0 : VitalDelayType01Z := UnitDelay01Z; -- tCD1, tCKHZ, tCKLZ tpd_CLKR_IOR0_PIPER_EQ_0 : VitalDelayType01Z := UnitDelay01Z; -- tCD2, tCKHZ, tCKLZ tpd_CLKR_IOR0_PIPER_EQ_1 : VitalDelayType01Z := UnitDelay01Z; -- tJCD tpd_TCK_TDO : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths -- tLC1 tpw_CLKR_PIPER_EQ_0_negedge : VitalDelayType := UnitDelay; -- tHC1 tpw_CLKR_PIPER_EQ_0_posedge : VitalDelayType := UnitDelay; -- tLC2 tpw_CLKR_PIPER_EQ_1_negedge : VitalDelayType := UnitDelay; -- tHC2 tpw_CLKR_PIPER_EQ_1_posedge : VitalDelayType := UnitDelay; -- tJCL tpw_TCK_negedge : VitalDelayType := UnitDelay; -- tJRST tpw_TRSTNeg_negedge : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq -- tCYC1 tperiod_CLKR_PIPER_EQ_0_posedge : VitalDelayType := UnitDelay; -- tCYC2 tperiod_CLKR_PIPER_EQ_1_posedge : VitalDelayType := UnitDelay; -- tJCYC tperiod_TCK_negedge : VitalDelayType := UnitDelay; -- trecovery values: release times -- tJRSR trecovery_TRSTNeg_TCK : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tSA tsetup_AL0_CLKL : VitalDelayType := UnitDelay; -- tSC tsetup_CE1L_CLKL : VitalDelayType := UnitDelay; -- tSW tsetup_RWL_CLKL : VitalDelayType := UnitDelay; -- tSD tsetup_IOL0_CLKL : VitalDelayType := UnitDelay; -- tSAD tsetup_ADSLNeg_CLKL : VitalDelayType := UnitDelay; -- tSCN tsetup_CNTENLNeg_CLKL : VitalDelayType := UnitDelay; -- tSRST tsetup_REPEATLNeg_CLKL : VitalDelayType := UnitDelay; -- tJS tsetup_TDI_TCK : VitalDelayType := UnitDelay; -- thold values: hold times -- tHA thold_AL0_CLKL : VitalDelayType := UnitDelay; -- tHC thold_CE1L_CLKL : VitalDelayType := UnitDelay; -- tHW thold_RWL_CLKL : VitalDelayType := UnitDelay; -- tHD thold_IOL0_CLKL : VitalDelayType := UnitDelay; -- tHAD thold_ADSLNeg_CLKL : VitalDelayType := UnitDelay; -- tHCN thold_CNTENLNeg_CLKL : VitalDelayType := UnitDelay; -- tHRST thold_REPEATLNeg_CLKL : VitalDelayType := UnitDelay; -- tJH thold_TDI_TCK : VitalDelayType := UnitDelay;⌨️ 快捷键说明
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