idt6167.vhd

vhdl cod for ram.For sp3e

            CONSTANT tsetup_A_WENeg : VitalDelayArrayType (HiAbit downto 0)
                              := (others => tsetup_A0_WENeg);

            CONSTANT thold_A_WENeg : VitalDelayArrayType (HiAbit downto 0)
                              := (others => thold_A0_WENeg);

            CONSTANT tsetup_D_WENeg : VitalDelayArrayType (HiDbit downto 0)
                              := (others => tsetup_A0_WENeg);

            CONSTANT thold_D_WENeg : VitalDelayArrayType (HiDbit downto 0)
                              := (others => thold_A0_WENeg);

            CONSTANT TDA : VitalDelayArrayType(HiAbit downto 0)
                              := (others => 0 ns);

            CONSTANT TDD : VitalDelayArrayType(HiDbit downto 0)
                              := (others => 0 ns);

            -- Timing Check Variables
            VARIABLE Tviol_A_WENeg: X01;
            VARIABLE TD_A_WENeg   : VitalMemoryTimingDataType
                                            := VitalMemoryTimingDataInit;

            VARIABLE Tviol_A_CENeg: X01;
            VARIABLE TD_A_CENeg   : VitalMemoryTimingDataType
                                            := VitalMemoryTimingDataInit;

            VARIABLE Tviol_D_WENeg: X01;
            VARIABLE TD_D_WENeg   : VitalMemoryTimingDataType
                                            := VitalMemoryTimingDataInit;

            VARIABLE Tviol_D_CENeg: X01 := '0';
            VARIABLE TD_D_CENeg   : VitalTimingDataType;

            VARIABLE Pviol_WENeg   : X01 := '0';
            VARIABLE PD_WENeg      : VitalPeriodDataType;

            -- VITAL Memory Declaration
            VARIABLE Memdat : VitalMemoryDataType :=
                VitalDeclareMemory (
                    NoOfWords            => TotalLOC,
                    NoOfBitsPerWord      => DataWidth,
                    NoOfBitsPerSubWord   => DataWidth,
--                    MemoryLoadFile       => MemLoadFileName,
                    BinaryLoadFile       => FALSE
                );

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';
            VARIABLE Q_zd     : std_logic_vector(HiDbit DOWNTO 0);

            VARIABLE Prevcntls    : std_logic_vector(0 to 1);
            VARIABLE PrevData     : std_logic_vector(HiDbit downto 0);
            VARIABLE Prevaddr     : std_logic_vector(HiAbit downto 0);
            VARIABLE PFlag        : VitalPortFlagVectorType(0 downto 0);
            VARIABLE Addrvalue    : VitalAddressValueType;
            VARIABLE WENegChange  : TIME := 0 ns;
            VARIABLE CENegChange  : TIME := 0 ns;
            VARIABLE AddrChangeArray  : VitalTimeArrayT(HiAbit downto 0);

            VARIABLE Q_GlitchData : VitalGlitchDataArrayType(HiDbit Downto 0);
            VARIABLE QSchedData   : VitalMemoryScheduleDataVectorType
                                    (HiDbit Downto 0);


        BEGIN 

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalMemorySetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => WENegIn,
                    RefSignalName   => "WENeg",
                    TestDelay       => TDA,
                    SetupHigh       => tsetup_A_WENeg,
                    SetupLow        => tsetup_A_WENeg,
                    HoldHigh        => thold_A_WENeg,
                    HoldLow         => thold_A_WENeg,
                    CheckEnabled    => (CENegIn = '0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_A_WENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    MsgFormat       => Vector,
                    Violation       => Tviol_A_WENeg );

                VitalMemorySetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => CENegIn,
                    RefSignalName   => "CENeg",
                    TestDelay       => TDA,
                    SetupHigh       => tsetup_A_WENeg,
                    SetupLow        => tsetup_A_WENeg,
                    HoldHigh        => thold_A_WENeg,
                    HoldLow         => thold_A_WENeg,
                    CheckEnabled    => (WENegIn = '0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_A_CENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    MsgFormat       => Vector,
                    Violation       => Tviol_A_CENeg );

                VitalMemorySetupHoldCheck (
                    TestSignal      => DataIn,
                    TestSignalName  => "Data",
                    RefSignal       => WENegIn,
                    RefSignalName   => "WENeg",
                    TestDelay       => TDD,
                    SetupHigh       => tsetup_D_WENeg,
                    SetupLow        => tsetup_D_WENeg,
                    HoldHigh        => thold_D_WENeg,
                    HoldLow         => thold_D_WENeg,
                    CheckEnabled    => (CENegIn = '0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D_WENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    MsgFormat       => Vector,
                    Violation       => Tviol_D_WENeg );

                VitalPeriodPulseCheck (
                    TestSignal      => WENegIn,
                    TestSignalName  => "WENeg",
                    PulseWidthLow   => tpw_WENeg_negedge,
                    PeriodData      => PD_WENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Pviol_WENeg,
                    HeaderMsg       => InstancePath & PartID,
                    CheckEnabled    => TRUE );

                Violation := Pviol_WENeg OR Tviol_D_WENeg OR Tviol_D_CENeg
                             OR Tviol_A_CENeg OR Tviol_A_WENeg;

                ASSERT Violation = '0'
                    REPORT InstancePath & partID & ": simulation may be" &
                           " inaccurate due to timing violations"
                    SEVERITY SeverityMode;

            END IF; -- Timing Check Section

            --------------------------------------------------------------------
            -- Functional Section
            --------------------------------------------------------------------
            VitalMemoryTable (
                DataOutBus     => Q_zd,
                MemoryData     => Memdat,
                PrevControls   => Prevcntls,
                PrevDataInBus  => Prevdata,
                PrevAddressBus => Prevaddr,
                PortFlag       => PFlag,
                Controls       => (CENegIn, WENegIn),
                DataInBus      => DataIn,
                AddressBus     => AddressIn,
                AddressValue   => Addrvalue,
                MemoryTable    => Table_2_cntrl_sram
            );

            --------------------------------------------------------------------
            -- Output Section
            --------------------------------------------------------------------
            VitalMemoryInitPathDelay (
                ScheduleDataArray   => QSchedData,
                OutputDataArray     => Q_zd
            );

            VitalMemoryAddPathDelay (
                ScheduleDataArray     => QSchedData,
                InputSignal           => WENegIn,
                OutputSignalName      => "Q",
                InputChangeTime       => WENegChange,
                PathDelayArray        => WENeg_Q_Delay,
                ArcType               => CrossArc,
                PathCondition         => CENegIn = '0',
                OutputRetainFlag      => false
            );

            VitalMemoryAddPathDelay (
                ScheduleDataArray     => QSchedData,
                InputSignal           => CENegIn,
                OutputSignalName      => "Q",
                InputChangeTime       => CENegChange,
                PathDelayArray        => CENeg_Q_Delay,
                ArcType               => CrossArc,
                PathCondition         => true,
                OutputRetainFlag      => false
            );

            VitalMemoryAddPathDelay (
                ScheduleDataArray     => QSchedData,
                InputSignal           => AddressIn,
                OutputSignalName      => "Q",
                InputChangeTimeArray  => AddrChangeArray,
                PathDelayArray        => Addr_Q_Delay,
                ArcType               => CrossArc,
                OutputRetainFlag      => true,
                OutputRetainBehavior  => BitCorrupt,
                PathCondition         => CENegIn = '0'
            );

            VitalMemorySchedulePathDelay (
                OutSignal            => QOut,
                OutputSignalName     => "Q",
                ScheduleDataArray   => QSchedData
            );

        END PROCESS;                           

    END BLOCK;
END vhdl_behavioral;