idt6167.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: idt6167.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2002 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Munden   02 MAR 24   Initial release
--    V1.1     R. Munden   02 DEC 28   Changed VITAL2000 to IEEE
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:     RAM
--  Technology:  CMOS
--  Part:        IDT6167
-- 
--  Description: 16K X 1 SRAM
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.vital_memory.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;
                USE FMF.memory.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY idt6167 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_WENeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_CENeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_D              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A13            : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        -- tWHZ
        tpd_WENeg_Q         : VitalDelayType01ZX := UnitDelay01ZX;
        -- tACS, tCLZ, tCHZ
        tpd_CENeg_Q         : VitalDelayType01ZX := UnitDelay01ZX;
        -- tAA, tOH
        tpd_A0_Q            : VitalDelayType01ZX := UnitDelay01ZX;
        -- tpw values: pulse widths
        -- tRC
        tpw_CENeg_negedge        : VitalDelayType    := UnitDelay;
        -- tWP
        tpw_WENeg_negedge        : VitalDelayType    := UnitDelay;
        -- tsetup values: setup times
        -- tAS
        tsetup_A0_WENeg          : VitalDelayType := UnitDelay;
        -- tDW
        tsetup_D_WENeg           : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        -- tWR
        thold_A0_WENeg           : VitalDelayType    := UnitDelay;
        -- tDH
        thold_D_WENeg            : VitalDelayType    := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXOn;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        MemLoadFileName     : STRING    := "idt6167.data";
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        A0              : IN    std_ulogic := 'U';
        A1              : IN    std_ulogic := 'U';
        A2              : IN    std_ulogic := 'U';
        A3              : IN    std_ulogic := 'U';
        A4              : IN    std_ulogic := 'U';
        A5              : IN    std_ulogic := 'U';
        A6              : IN    std_ulogic := 'U';
        A7              : IN    std_ulogic := 'U';
        A8              : IN    std_ulogic := 'U';
        A9              : IN    std_ulogic := 'U';
        A10             : IN    std_ulogic := 'U';
        A11             : IN    std_ulogic := 'U';
        A12             : IN    std_ulogic := 'U';
        A13             : IN    std_ulogic := 'U';
        D               : IN    std_ulogic := 'U';
        Q               : OUT   std_ulogic := 'U';
        WENeg           : IN    std_ulogic := 'U';
        CENeg           : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of idt6167 : ENTITY IS TRUE;
END idt6167;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt6167 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "IDT6167";
    CONSTANT MaxData        : NATURAL := 1;
    CONSTANT TotalLOC       : NATURAL := 16383;
    CONSTANT HiAbit         : NATURAL := 13;
    CONSTANT HiDbit         : NATURAL := 0;
    CONSTANT DataWidth      : NATURAL := 1;
    CONSTANT DlyArraySize   : NATURAL := 14;

    SIGNAL D_ipd            : std_ulogic := 'U';

    SIGNAL A0_ipd           : std_ulogic := 'U';
    SIGNAL A1_ipd           : std_ulogic := 'U';
    SIGNAL A2_ipd           : std_ulogic := 'U';
    SIGNAL A3_ipd           : std_ulogic := 'U';
    SIGNAL A4_ipd           : std_ulogic := 'U';
    SIGNAL A5_ipd           : std_ulogic := 'U';
    SIGNAL A6_ipd           : std_ulogic := 'U';
    SIGNAL A7_ipd           : std_ulogic := 'U';
    SIGNAL A8_ipd           : std_ulogic := 'U';
    SIGNAL A9_ipd           : std_ulogic := 'U';
    SIGNAL A10_ipd          : std_ulogic := 'U';
    SIGNAL A11_ipd          : std_ulogic := 'U';
    SIGNAL A12_ipd          : std_ulogic := 'U';
    SIGNAL A13_ipd          : std_ulogic := 'U';

    SIGNAL WENeg_ipd        : std_ulogic := 'U';
    SIGNAL CENeg_ipd        : std_ulogic := 'U';


BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_2: VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
        w_3: VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg);
        w_5: VitalWireDelay (D_ipd, D, tipd_D);
        w_13: VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_14: VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_15: VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_16: VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_17: VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_18: VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_19: VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_20: VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_21: VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_22: VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_23: VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_24: VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_25: VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_26: VitalWireDelay (A13_ipd, A13, tipd_A13);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            AddressIn       : IN    std_logic_vector(HiAbit downto 0);
            DataIn          : IN    std_logic_vector(HiDbit downto 0);
            QOut            : OUT   std_logic_vector(HiDbit downto 0);
            WENegIn         : IN    std_ulogic := 'U';
            CENegIn         : IN    std_ulogic := 'U'
        );
        PORT MAP (
            QOut(0)      =>  Q,
            DataIn(0)    => to_UX01(D_ipd),
            AddressIn(0) => A0_ipd,
            AddressIn(1) => A1_ipd,
            AddressIn(2) => A2_ipd,
            AddressIn(3) => A3_ipd,
            AddressIn(4) => A4_ipd,
            AddressIn(5) => A5_ipd,
            AddressIn(6) => A6_ipd,
            AddressIn(7) => A7_ipd,
            AddressIn(8) => A8_ipd,
            AddressIn(9) => A9_ipd,
            AddressIn(10) => A10_ipd,
            AddressIn(11) => A11_ipd,
            AddressIn(12) => A12_ipd,
            AddressIn(13) => A13_ipd,
            WENegIn => to_UX01(WENeg_ipd),
            CENegIn => to_UX01(CENeg_ipd)
        );

    BEGIN 

        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Behavior : PROCESS (WENegIn, CENegIn, AddressIn,
                            DataIn)
                         
            CONSTANT WENeg_Q_Delay :VitalDelayArrayType01ZX
                      (HiDbit downto 0) := (OTHERS => tpd_WENeg_Q);

            CONSTANT CENeg_Q_Delay :VitalDelayArrayType01ZX
                      (HiDbit downto 0) := (OTHERS => tpd_CENeg_Q);

            CONSTANT Addr_Q_Delay : VitalDelayArrayType01ZX
                      (DlyArraySize downto 0) := (OTHERS => tpd_A0_Q);