cy7c1362.vhd

vhdl cod for ram.For sp3e

                        OBuf1 := (OTHERS => 'Z');
                        OBuf2 := (OTHERS => 'Z');
                    WHEN begin_rw  | SCrd =>
                        IF command = begin_rw THEN
                            state <= begin_rdwr;
                        ELSE
                            state <= SCread;
                        END IF;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 DOWNTO 0));
                        Mem_read;
                    WHEN SCwr =>
                        state <= SCwrite;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 DOWNTO 0));
                        OBuf1 := (OTHERS => 'Z');
                        Mem_write;
                    WHEN SPwr_burst =>
                        OBuf1 := (OTHERS => 'Z');
                        OBuf2 := (OTHERS => 'Z');
                    WHEN SPwr_susp =>
                        IF state = begin_rdwr THEN
                            state <= SPwrite;
                            OBuf1 := (OTHERS => 'Z');
                            OBuf2 := (OTHERS => 'Z');
                            Mem_write;
                        END IF;
                    WHEN read_burst =>
                        state <= read;
                        Burst_Cnt := Burst_Cnt + 1;
                        offset := Burst_Seq(memstart)(Burst_Cnt);
                        MemAddr := startaddr + offset;
                        Mem_read;
                    WHEN read_susp =>
                        OBuf1 := (OTHERS => 'Z');
                END CASE;

            WHEN SPwrite =>
                CASE command IS
                    WHEN ds =>
                        state <= desel;
                        OBuf1 := (OTHERS => 'Z');
                        OBuf2 := (OTHERS => 'Z');
                    WHEN begin_rw  | SCrd =>
                        IF command = begin_rw THEN
                            state <= begin_rdwr;
                        ELSE
                            state <= SCread;
                        END IF;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 DOWNTO 0));
                        Mem_read;
                    WHEN SCwr =>
                        state <= SCwrite;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 DOWNTO 0));
                        OBuf1 := (OTHERS => 'Z');
                        Mem_write;
                    WHEN SPwr_burst =>
                        state <= SPwrite;
                        Burst_Cnt := Burst_Cnt + 1;
                        IF (Burst_Cnt = 4) THEN
                            Burst_Cnt := 0;
                        END IF;
                        offset := Burst_Seq(memstart)(Burst_Cnt);
                        MemAddr := startaddr + offset;
                        OBuf1 := (OTHERS => 'Z');
                        Mem_write;
                    WHEN SPwr_susp =>
                        state <= SPwrite;
                        OBuf1 := (OTHERS => 'Z');
                        Mem_write;
                    WHEN read_burst =>
                        OBuf1 := (OTHERS => 'Z');
                        OBuf2 := (OTHERS => 'Z');
                    WHEN read_susp =>
                        OBuf1 := (OTHERS => 'Z');
                        OBuf2 := (OTHERS => 'Z');
                END CASE;

            WHEN SCwrite =>
                Burst_Cnt := 0;
                CASE command IS
                    WHEN ds =>
                        state <= desel;
                        OBuf1 := (OTHERS => 'Z');
                        OBuf2 := (OTHERS => 'Z');
                    WHEN begin_rw  | SCrd =>
                        IF command = begin_rw THEN
                            state <= begin_rdwr;
                        ELSE
                            state <= SCread;
                        END IF;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 DOWNTO 0));
                        Mem_read;
                    WHEN SCwr =>
                        state <= SCwrite;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 DOWNTO 0));
                        OBuf1 := (OTHERS => 'Z');
                        Mem_write;
                    WHEN SPwr_burst =>
                        state <= SPwrite;
                        Burst_Cnt := Burst_Cnt + 1;
                        offset := Burst_Seq(memstart)(Burst_Cnt);
                        MemAddr := startaddr + offset;
                        OBuf1 := (OTHERS => 'Z');
                        Mem_write;
                    WHEN SPwr_susp =>
                        OBuf1 := (OTHERS => 'Z');
                    WHEN read_burst =>
                        OBuf1 := (OTHERS => 'Z');
                        OBuf2 := (OTHERS => 'Z');
                    WHEN read_susp =>
                        OBuf1 := (OTHERS => 'Z');
                        OBuf2 := (OTHERS => 'Z');
                END CASE;

            WHEN read =>
                CASE command IS
                    WHEN ds =>
                        state <= desel;
                        OBuf1 := (OTHERS => 'Z');
                        OBuf2 := (OTHERS => 'Z');
                    WHEN begin_rw  | SCrd =>
                        IF command = begin_rw THEN
                            state <= begin_rdwr;
                        ELSE
                            state <= SCread;
                        END IF;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 DOWNTO 0));
                        Mem_read;
                    WHEN SCwr =>
                        state <= SCwrite;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 DOWNTO 0));
                        OBuf1 := (OTHERS => 'Z');
                        Mem_write;
                    WHEN SPwr_burst =>
                        OBuf1 := (OTHERS => 'Z');
                        OBuf2 := (OTHERS => 'Z');
                    WHEN SPwr_susp =>
                        OBuf1 := (OTHERS => 'Z');
                        OBuf2 := (OTHERS => 'Z');
                    WHEN read_burst =>
                        state <= read;
                        Burst_Cnt := Burst_Cnt + 1;
                        IF (Burst_Cnt = 4) THEN
                            Burst_Cnt := 0;
                        END IF;
                        offset := Burst_Seq(memstart)(Burst_Cnt);
                        MemAddr := startaddr + offset;
                        Mem_read;
                    WHEN read_susp =>
                        state <= read;
                END CASE;
        END CASE;

        IF (OENegIn = '0') THEN
           D_zd <= OBuf2;
        END IF;

    END IF;

    IF (OENegIn = '1') THEN
        D_zd <= (OTHERS => 'Z');
    ELSIF falling_edge(OENegIn) AND (ZZIn = '0') AND zz_reset THEN
        D_zd <= OBuf2;
    END IF;

    IF rising_edge(ZZIn) THEN
        IF zz_reset THEN
            IF state = desel THEN
                zz_start := TRUE;
                zz_false := FALSE;
            ELSE
                zz_start := FALSE;
                count := 0;
                zz_false := TRUE;
                ASSERT false
                    REPORT InstancePath & partID & "The device must be " &
                           "deselected prior to entering the sleep mode."
                    SEVERITY SeverityMode;
            END IF;
        ELSE
            zz_stop := FALSE;
            count := 0;
            ASSERT false
                REPORT InstancePath & partID & ": 2tCYC are "
                       &  "required to exit from sleep mode."
                SEVERITY SeverityMode;
        END IF;
    ELSIF falling_edge(ZZIn) THEN
        IF zz_reset THEN
            zz_start := FALSE;
            count := 0;
            IF NOT zz_false THEN
                ASSERT false
                    REPORT InstancePath & partID & ": 2tCYC are "
                           & "required to enter into sleep mode."
                    SEVERITY SeverityMode;
            END IF;
        ELSE
            zz_stop := TRUE;
        END IF;
    END IF;

    IF rising_edge(CLKIn) THEN
        IF zz_start THEN
            IF count < 2 THEN
                count := count + 1;
            ELSE
                zz_reset := FALSE;
                zz_start := FALSE;
                count := 0;
            END IF;
        END IF;
        IF zz_stop THEN
            IF count < 2 THEN
                count := count + 1;
            ELSE
                zz_reset := TRUE;
                zz_stop := FALSE;
                count := 0;
            END IF;
        END IF;
    END IF;

    IF NOT zz_reset AND zz_stop AND (CE2In = '1' OR CE1NegIn = '0'
    OR CE3NegIn = '0' OR ADSPNIn = '0' OR ADSCNIn = '0') THEN
        ASSERT FALSE
            REPORT InstancePath & partID & ": CEs, ADSC and ADSP must " &
            "remain inactive for the duration of tZZREC after the ZZ " &
            "input returns LOW."
        SEVERITY SeverityMode;
    END IF;

    END PROCESS;

    ------------------------------------------------------------------------
    -- Path Delay Process
    ------------------------------------------------------------------------
    DataOutPath : FOR I IN 17 DOWNTO 0 GENERATE
        DataOut_Delay : PROCESS (D_zd(i))
            VARIABLE D_GlitchData:VitalGlitchDataArrayType(17 Downto 0);
        BEGIN
            VitalPathDelay01Z (
                OutSignal       => DataOut(i),
                OutSignalName   => "Data",
                OutTemp         => D_zd(i),
                Mode            => VitalTransport,
                GlitchData      => D_GlitchData(i),
                Paths           => (
                0 => (InputChangeTime => CLKIn'LAST_EVENT,
                      PathDelay => tpd_CLK_DQA0,
                      PathCondition   => OENegIn = '0' AND CLKIn = '1'),
                1 => (InputChangeTime => OENegIn'LAST_EVENT,
                      PathDelay => tpd_OENeg_DQA0,
                      PathCondition   => TRUE)
                )
            );
        END PROCESS;
    END GENERATE;

    --------------------------------------------------------------------------
    -- File Read Section
    --------------------------------------------------------------------------
    --cy7c1362 memory file
    --@aaaaa    - <aaaaa> stands for address
    --ddddd     - <ddddd> is word to be written at MemDataA,B(aaaaa++)
    --(aaaaa is incremented at every load)
    --(ddddd is a 18-bit data, MemDataA(aaaaa++) is loaded with the lowest
    --nine bits, MemDataB(aaaaa++) is loaded with the next nine LSBs)
    --only first 1-6 columns are loaded. NO empty lines !!!!!!!!!!!!!!!!
    default: PROCESS IS

        VARIABLE ind        : NATURAL := 0;
        VARIABLE linecnt    : NATURAL := 0;
        VARIABLE buf        : line;

    BEGIN
        IF (mem_file_name /= "none") AND (NOW < 1 ns) THEN
            ind := 0;
            linecnt := 0;
            WHILE (NOT ENDFILE (mem_file)) LOOP
                READLINE (mem_file, buf);
                linecnt := linecnt +1;
                IF buf(1) = '/' THEN     --comment
                    NEXT;
                ELSIF buf(1) = '@' THEN  --address
                    ind := h(buf(2 TO 6));
                ELSE
                    IF ind <= MemSize THEN
                        MemDataA(ind) := (h(buf(3 TO 5)) MOD 512);
                        MemDataB(ind) := (h(buf(1 TO 3)) MOD 1024)/2;
                        ind := ind + 1;
                    ELSE
                        ASSERT FALSE
                        REPORT "file: "&mem_file_name&" has size larger than "
                        &to_int_str(MemSize+1)&" at line "&to_int_str(linecnt)
                        SEVERITY warning;
                    END IF;
                END IF;
            END LOOP;
        END IF;
        WAIT;
    END PROCESS default;

    END BLOCK;

END vhdl_behavioral;