cy7c1362.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: cy7c1362.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:         | mod date: | changes made:
--    V1.0     M. Milanovic       05 Nov 30   Initial Release
--
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:     RAM
--  Technology:  CMOS
--  Part:        CY7C1362
--
--  Description: 512K x 18 Pipelined Burst SRAM
--------------------------------------------------------------------------------
--  Comments :
--      For correct simulation, simulator resolution should be set to 1ps
--------------------------------------------------------------------------------

LIBRARY IEEE;     USE IEEE.std_logic_1164.ALL;
                  USE IEEE.VITAL_timing.ALL;
                  USE IEEE.VITAL_primitives.ALL;

                  USE STD.textio.ALL;
LIBRARY FMF;      USE FMF.gen_utils.ALL;
                  USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY cy7c1362 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A13                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A14                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A15                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A16                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A17                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A18                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQA0                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQA1                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQA2                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQA3                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQA4                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQA5                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQA6                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQA7                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQA8                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQB0                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQB1                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQB2                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQB3                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQB4                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQB5                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQB6                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQB7                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQB8                : VitalDelayType01 := VitalZeroDelay01;
        tipd_BWANeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_BWBNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_GWNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_BWENeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CE1Neg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CE2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CE3Neg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_ADVNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_ADSPNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_ADSCNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_MODE                : VitalDelayType01 := VitalZeroDelay01;
        tipd_ZZ                  : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLK_DQA0             : VitalDelayType01Z := UnitDelay01Z;
        tpd_OENeg_DQA0           : VitalDelayType01Z := UnitDelay01Z;
        -- tpw values: pulse widths
        tpw_CLK_posedge        : VitalDelayType := UnitDelay;
        tpw_CLK_negedge        : VitalDelayType := UnitDelay;
        -- tperiod min (calculated as 1/max freq)
        tperiod_CLK_posedge    : VitalDelayType := UnitDelay;
        -- tsetup values: setup times
        tsetup_A0_CLK           : VitalDelayType := UnitDelay;
        tsetup_DQA0_CLK         : VitalDelayType := UnitDelay;
        tsetup_ADVNeg_CLK       : VitalDelayType := UnitDelay;
        tsetup_ADSCNeg_CLK      : VitalDelayType := UnitDelay;
        tsetup_CE2_CLK          : VitalDelayType := UnitDelay;
        tsetup_BWANeg_CLK       : VitalDelayType := UnitDelay;
        -- thold values: hold times
        thold_A0_CLK            : VitalDelayType := UnitDelay;
        thold_DQA0_CLK          : VitalDelayType := UnitDelay;
        thold_ADVNeg_CLK        : VitalDelayType := UnitDelay;
        thold_ADSCNeg_CLK       : VitalDelayType := UnitDelay;
        thold_CE2_CLK           : VitalDelayType := UnitDelay;
        thold_BWANeg_CLK        : VitalDelayType := UnitDelay;
        -- generic control parameters
        InstancePath        : string    := DefaultInstancePath;
        TimingChecksOn      : boolean   := DefaultTimingChecks;
        MsgOn               : boolean   := DefaultMsgOn;
        XOn                 : boolean   := DefaultXon;
        SeverityMode        : severity_level := warning;
        -- memory file to be loaded
        mem_file_name       : STRING    := "cy7c1362.mem";
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        A0              : IN    std_logic := 'U';
        A1              : IN    std_logic := 'U';
        A2              : IN    std_logic := 'U';
        A3              : IN    std_logic := 'U';
        A4              : IN    std_logic := 'U';
        A5              : IN    std_logic := 'U';
        A6              : IN    std_logic := 'U';
        A7              : IN    std_logic := 'U';
        A8              : IN    std_logic := 'U';
        A9              : IN    std_logic := 'U';
        A10             : IN    std_logic := 'U';
        A11             : IN    std_logic := 'U';
        A12             : IN    std_logic := 'U';
        A13             : IN    std_logic := 'U';
        A14             : IN    std_logic := 'U';
        A15             : IN    std_logic := 'U';
        A16             : IN    std_logic := 'U';
        A17             : IN    std_logic := 'U';
        A18             : IN    std_logic := 'U';
        DQA0            : INOUT std_logic := 'U';
        DQA1            : INOUT std_logic := 'U';
        DQA2            : INOUT std_logic := 'U';
        DQA3            : INOUT std_logic := 'U';
        DQA4            : INOUT std_logic := 'U';
        DQA5            : INOUT std_logic := 'U';
        DQA6            : INOUT std_logic := 'U';
        DQA7            : INOUT std_logic := 'U';
        DQA8            : INOUT std_logic := 'U';
        DQB0            : INOUT std_logic := 'U';
        DQB1            : INOUT std_logic := 'U';
        DQB2            : INOUT std_logic := 'U';
        DQB3            : INOUT std_logic := 'U';
        DQB4            : INOUT std_logic := 'U';
        DQB5            : INOUT std_logic := 'U';
        DQB6            : INOUT std_logic := 'U';
        DQB7            : INOUT std_logic := 'U';
        DQB8            : INOUT std_logic := 'U';
        BWANeg          : IN    std_logic := 'U';
        BWBNeg          : IN    std_logic := 'U';
        GWNeg           : IN    std_logic := 'U';
        BWENeg          : IN    std_logic := 'U';
        CLK             : IN    std_logic := 'U';
        CE1Neg          : IN    std_logic := 'U';
        CE2             : IN    std_logic := 'U';
        CE3Neg          : IN    std_logic := 'U';
        OENeg           : IN    std_logic := 'U';
        ADVNeg          : IN    std_logic := 'U';
        ADSPNeg         : IN    std_logic := 'U';
        ADSCNeg         : IN    std_logic := 'U';
        MODE            : IN    std_logic := 'U';
        ZZ              : IN    std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 OF cy7c1362 : ENTITY IS TRUE;
END cy7c1362;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF cy7c1362 IS
    ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID           : STRING := "CY7C1362";
    -- ipd
    SIGNAL A0_ipd              : std_ulogic := 'U';
    SIGNAL A1_ipd              : std_ulogic := 'U';
    SIGNAL A2_ipd              : std_ulogic := 'U';
    SIGNAL A3_ipd              : std_ulogic := 'U';
    SIGNAL A4_ipd              : std_ulogic := 'U';
    SIGNAL A5_ipd              : std_ulogic := 'U';
    SIGNAL A6_ipd              : std_ulogic := 'U';
    SIGNAL A7_ipd              : std_ulogic := 'U';
    SIGNAL A8_ipd              : std_ulogic := 'U';
    SIGNAL A9_ipd              : std_ulogic := 'U';
    SIGNAL A10_ipd             : std_ulogic := 'U';
    SIGNAL A11_ipd             : std_ulogic := 'U';
    SIGNAL A12_ipd             : std_ulogic := 'U';
    SIGNAL A13_ipd             : std_ulogic := 'U';
    SIGNAL A14_ipd             : std_ulogic := 'U';
    SIGNAL A15_ipd             : std_ulogic := 'U';
    SIGNAL A16_ipd             : std_ulogic := 'U';
    SIGNAL A17_ipd             : std_ulogic := 'U';
    SIGNAL A18_ipd             : std_ulogic := 'U';
    SIGNAL DQA0_ipd            : std_ulogic := 'U';
    SIGNAL DQA1_ipd            : std_ulogic := 'U';
    SIGNAL DQA2_ipd            : std_ulogic := 'U';
    SIGNAL DQA3_ipd            : std_ulogic := 'U';
    SIGNAL DQA4_ipd            : std_ulogic := 'U';
    SIGNAL DQA5_ipd            : std_ulogic := 'U';
    SIGNAL DQA6_ipd            : std_ulogic := 'U';
    SIGNAL DQA7_ipd            : std_ulogic := 'U';
    SIGNAL DQA8_ipd            : std_ulogic := 'U';
    SIGNAL DQB0_ipd            : std_ulogic := 'U';
    SIGNAL DQB1_ipd            : std_ulogic := 'U';
    SIGNAL DQB2_ipd            : std_ulogic := 'U';
    SIGNAL DQB3_ipd            : std_ulogic := 'U';
    SIGNAL DQB4_ipd            : std_ulogic := 'U';
    SIGNAL DQB5_ipd            : std_ulogic := 'U';
    SIGNAL DQB6_ipd            : std_ulogic := 'U';
    SIGNAL DQB7_ipd            : std_ulogic := 'U';
    SIGNAL DQB8_ipd            : std_ulogic := 'U';
    SIGNAL BWANeg_ipd          : std_ulogic := 'U';
    SIGNAL BWBNeg_ipd          : std_ulogic := 'U';
    SIGNAL GWNeg_ipd           : std_ulogic := 'U';
    SIGNAL BWENeg_ipd          : std_ulogic := 'U';
    SIGNAL CLK_ipd             : std_ulogic := 'U';
    SIGNAL CE1Neg_ipd          : std_ulogic := 'U';
    SIGNAL CE2_ipd             : std_ulogic := 'U';
    SIGNAL OENeg_ipd           : std_ulogic := 'U';
    SIGNAL CE3Neg_ipd          : std_ulogic := 'U';
    SIGNAL ADVNeg_ipd          : std_ulogic := 'U';
    SIGNAL ADSPNeg_ipd         : std_ulogic := 'U';
    SIGNAL ADSCNeg_ipd         : std_ulogic := 'U';
    SIGNAL MODE_ipd            : std_ulogic := 'U';
    SIGNAL ZZ_ipd              : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_2 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_3 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_4 : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_5 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_6 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_7 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_8 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_9 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_10 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_11 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_12 : VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_13 : VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_14 : VitalWireDelay (A13_ipd, A13, tipd_A13);
        w_15 : VitalWireDelay (A14_ipd, A14, tipd_A14);
        w_16 : VitalWireDelay (A15_ipd, A15, tipd_A15);
        w_17 : VitalWireDelay (A16_ipd, A16, tipd_A16);
        w_18 : VitalWireDelay (A17_ipd, A17, tipd_A17);
        w_19 : VitalWireDelay (A18_ipd, A18, tipd_A18);
        w_20 : VitalWireDelay (DQA0_ipd, DQA0, tipd_DQA0);
        w_21 : VitalWireDelay (DQA1_ipd, DQA1, tipd_DQA1);
        w_22 : VitalWireDelay (DQA2_ipd, DQA2, tipd_DQA2);
        w_23 : VitalWireDelay (DQA3_ipd, DQA3, tipd_DQA3);
        w_24 : VitalWireDelay (DQA4_ipd, DQA4, tipd_DQA4);
        w_25 : VitalWireDelay (DQA5_ipd, DQA5, tipd_DQA5);
        w_26 : VitalWireDelay (DQA6_ipd, DQA6, tipd_DQA6);
        w_27 : VitalWireDelay (DQA7_ipd, DQA7, tipd_DQA7);
        w_28 : VitalWireDelay (DQA8_ipd, DQA8, tipd_DQA8);
        w_29 : VitalWireDelay (DQB0_ipd, DQB0, tipd_DQB0);
        w_30 : VitalWireDelay (DQB1_ipd, DQB1, tipd_DQB1);
        w_31 : VitalWireDelay (DQB2_ipd, DQB2, tipd_DQB2);
        w_32 : VitalWireDelay (DQB3_ipd, DQB3, tipd_DQB3);
        w_33 : VitalWireDelay (DQB4_ipd, DQB4, tipd_DQB4);
        w_34 : VitalWireDelay (DQB5_ipd, DQB5, tipd_DQB5);
        w_35 : VitalWireDelay (DQB6_ipd, DQB6, tipd_DQB6);
        w_36 : VitalWireDelay (DQB7_ipd, DQB7, tipd_DQB7);
        w_37 : VitalWireDelay (DQB8_ipd, DQB8, tipd_DQB8);
        w_38 : VitalWireDelay (BWANeg_ipd, BWANeg, tipd_BWANeg);
        w_39 : VitalWireDelay (BWBNeg_ipd, BWBNeg, tipd_BWBNeg);
        w_40 : VitalWireDelay (GWNeg_ipd, GWNeg, tipd_GWNeg);
        w_41 : VitalWireDelay (BWENeg_ipd, BWENeg, tipd_BWENeg);
        w_42 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_43 : VitalWireDelay (CE1Neg_ipd, CE1Neg, tipd_CE1Neg);
        w_44 : VitalWireDelay (CE2_ipd, CE2, tipd_CE2);
        w_45 : VitalWireDelay (CE3Neg_ipd, CE3Neg, tipd_CE3Neg);
        w_46 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);
        w_47 : VitalWireDelay (ADVNeg_ipd, ADVNeg, tipd_ADVNeg);
        w_48 : VitalWireDelay (ADSPNeg_ipd, ADSPNeg, tipd_ADSPNeg);
        w_49 : VitalWireDelay (ADSCNeg_ipd, ADSCNeg, tipd_ADSCNeg);
        w_50 : VitalWireDelay (MODE_ipd, MODE, tipd_MODE);
        w_51 : VitalWireDelay (ZZ_ipd, ZZ, tipd_ZZ);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            BWANIn          : IN    std_ulogic := 'U';
            BWBNIn          : IN    std_ulogic := 'U';
            GWNIn           : IN    std_ulogic := 'U';
            BWENIn          : IN    std_ulogic := 'U';
            DatAIn          : IN    std_logic_vector(8 DOWNTO 0);
            DatBIn          : IN    std_logic_vector(8 DOWNTO 0);
            DataOut         : OUT   std_logic_vector(17 DOWNTO 0)
                                                     := (OTHERS => 'Z');
            CLKIn           : IN    std_ulogic := 'U';
            AddressIn       : IN    std_logic_vector(18 DOWNTO 0);
            OENegIn         : IN    std_ulogic := 'U';
            ADVNIn          : IN    std_ulogic := 'U';
            ADSPNIn         : IN    std_ulogic := 'U';