xc18v04.ftm
来自「vhdl cod for ram.For sp3e」· FTM 代码 · 共 49 行
FTM
49 行
<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for xc1804 Parts</TITLE><REVISION.HISTORY>version: | author: | mod date: | changes made: V1.0 D.Stanojkovic 07 Oct 09 Initial release</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>xc18v04</MODEL><FMFTIME>XC18V04VQ44C<SOURCE>Xilinx, DS026 (v5.1.0) March 6, 2006</SOURCE>XC18V04VQG44C<SOURCE>Xilinx, DS026 (v5.1.0) March 6, 2006</SOURCE>XC18V04PC44C<SOURCE>Xilinx, DS026 (v5.1.0) March 6, 2006</SOURCE>XC18V04PCG44C<SOURCE>Xilinx, DS026 (v5.1.0) March 6, 2006</SOURCE><COMMENT>The values listed are for VCC=3.0V to 3.6V, CL=50pF, Ta=-40 to +85 Celsius</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RESETNeg D0 () () (8:17:25) (3:7:10) (8:17:25) (3:7:10)) (IOPATH CENeg D0 () () (8:17:25) (7:13:20) (8:17:25) (7:13:20)) (IOPATH CLK D0 (7:13:20) (7:13:20)) (IOPATH TCK TDO (8:17:25) (8:17:25)) )) (TIMINGCHECK (SETUP CENeg CLK (25)) (SETUP TMS TCK (10)) (SETUP TDI TCK (10)) (HOLD TMS TCK (25)) (HOLD TDI TCK (25)) (WIDTH (posedge CLK) (10)) (WIDTH (negedge CLK) (10)) (WIDTH (posedge CENeg) (250)) (WIDTH (negedge RESETNeg) (250)) (PERIOD CLK (50)) (PERIOD (COND BYPSS == 0 TCK) (100)) (PERIOD (COND BYPSS == 1 TCK) (50)))) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/VCC) (DELAY (ABSOLUTE (DEVICE(200000:1000000:50000000))))) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/OER) (DELAY (ABSOLUTE (DEVICE(1000000:1000000:1000000))))) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/ISP) (DELAY (ABSOLUTE (DEVICE(14000000:14000000:14000000))))) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/ERS) (DELAY (ABSOLUTE (DEVICE(15000000000:15000000000:15000000000))))</TIMING></FMFTIME></BODY></FTML>⌨️ 快捷键说明
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