📄 mt48lc16m16a2.vhd
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ELSIF (command = writ) THEN ASSERT rcdt_out(bank) = '0' REPORT InstancePath & partID & BankString & ": write command" & " received too soon after active." SEVERITY SeverityMode; ASSERT ((AddressIn(10) = '0') OR (AddressIn(10) = '1')) REPORT InstancePath & partID & BankString & ": AddressIn(10) = X" & " during write command. Next state unknown." SEVERITY SeverityMode; MemAddr(bank)(9 downto 0) := (others => '0'); -- clr old addr MemAddr(bank)(9 downto Burst_Bits) := AddressIn(9 downto Burst_Bits); --latch col addr IF (Burst_Bits > 0) THEN Burst_Inc(bank) := to_nat(AddressIn(Burst_Bits-1 downto 0)); END IF; StartAddr(bank) := Burst_Inc(bank) mod 8; BaseLoc(bank) := to_nat(MemAddr(bank)); Location := 2*(BaseLoc(bank) + Burst_Inc(bank)); IF (DQML_nwv = '0') THEN MemData(Bank)(Location) := -1; IF Violation = '0' THEN MemData(Bank)(Location) := to_nat(DataIn(7 downto 0)); END IF; END IF; IF (DQMH_nwv = '0') THEN MemData(Bank)(Location+1) := -1; IF Violation = '0' THEN MemData(Bank)(Location+1) := to_nat(DataIn(15 downto 8)); END IF; END IF; Burst_Cnt(bank) := 1; wrt_in <= '1'; IF (AddressIn(10) = '0') THEN statebank(bank) <= write; ELSIF (AddressIn(10) = '1') THEN statebank(bank) <= write_auto_pre; END IF; written := true; ELSIF (cur_bank = bank) OR (command = mrs) THEN ASSERT false REPORT InstancePath & partID & BankString & ": Illegal command " & "received in active state." SEVERITY SeverityMode; END IF; WHEN write => IF (command = bst) THEN statebank(bank) <= bank_act; Burst_Cnt(bank) := 0; ELSIF (command = read) THEN IF (bank = cur_bank) THEN MemAddr(bank)(9 downto 0) := (others => '0'); -- clr old addr MemAddr(bank)(9 downto Burst_Bits) := AddressIn(9 downto Burst_Bits); --latch col addr IF (Burst_Bits > 0) THEN Burst_Inc(bank) := to_nat(AddressIn(Burst_Bits-1 downto 0)); END IF; StartAddr(bank) := Burst_Inc(bank) mod 8; BaseLoc(bank) := to_nat(MemAddr(bank)); Location := 2*(BaseLoc(bank) + Burst_Inc(bank)); DataDrive(7 downto 0) := (others => 'U'); IF MemData(Bank)(Location) > -2 THEN DataDrive(7 downto 0) := (others => 'X'); END IF; IF MemData(Bank)(Location) > -1 THEN DataDrive(7 downto 0):= to_slv(MemData(Bank)(Location),8); END IF; DataDrive(15 downto 8) := (others => 'U'); IF MemData(Bank)(Location+1) > -2 THEN DataDrive(15 downto 8) := (others => 'X'); END IF; IF MemData(Bank)(Location+1) > -1 THEN DataDrive(15 downto 8):= to_slv(MemData(Bank)(Location+1),8); END IF; Burst_Cnt(bank) := 1; IF (AddressIn(10) = '0') THEN statebank(bank) <= read; ELSIF (AddressIn(10) = '1') THEN statebank(bank) <= read_auto_pre; END IF; ELSE statebank(bank) <= bank_act; END IF; ELSIF (command = writ) THEN IF cur_bank = bank THEN MemAddr(bank)(9 downto 0) := (others => '0'); -- clr old addr MemAddr(bank)(9 downto Burst_Bits) := AddressIn(9 downto Burst_Bits); --latch col addr IF (Burst_Bits > 0) THEN Burst_Inc(bank) := to_nat(AddressIn(Burst_Bits-1 downto 0)); END IF; StartAddr(bank) := Burst_Inc(bank) mod 8; BaseLoc(bank) := to_nat(MemAddr(bank)); Location := 2*(BaseLoc(bank) + Burst_Inc(bank)); IF (DQML_nwv = '0') THEN MemData(Bank)(Location) := -1; IF Violation = '0' THEN MemData(Bank)(Location) := to_nat(DataIn(7 downto 0)); END IF; END IF; IF (DQMH_nwv = '0') THEN MemData(Bank)(Location+1) := -1; IF Violation = '0' THEN MemData(Bank)(Location+1) := to_nat(DataIn(15 downto 8)); END IF; END IF; Burst_Cnt(bank) := 1; wrt_in <= '1'; IF (AddressIn(10) = '1') THEN statebank(bank) <= write_auto_pre; END IF; ELSE statebank(bank) <= bank_act; END IF; ELSIF (command = pre) AND ((cur_bank = bank) OR (AddressIn(10) = '1')) THEN ASSERT ras_out(bank) = '1' REPORT InstancePath & partID & BankString & ": precharge command" & " does not meet tRAS time." SEVERITY SeverityMode; ASSERT (DQML_nwv = '1') REPORT InstancePath & partID & BankString & ": DQML should be" & " held high, data is lost." SEVERITY SeverityMode; ASSERT (DQMH_nwv = '1') REPORT InstancePath & partID & BankString & ": DQMH should be" & " held high, data is lost." SEVERITY SeverityMode; statebank(bank) <= precharge, idle AFTER tdevice_TRP; ELSIF (command = nop) OR (cur_bank /= bank) THEN IF (Burst_Cnt(bank) = Burst_Length OR WB = single) THEN statebank(bank) <= bank_act; Burst_Cnt(bank) := 0; ras_in(bank) <= '1'; ELSE IF (Burst = sequential) THEN Burst_Inc(bank) := (Burst_Inc(bank) + 1) MOD Burst_Length; ELSE Burst_Inc(bank) := intab(StartAddr(bank)) (Burst_Cnt(bank)); END IF; Location := 2*(BaseLoc(bank) + Burst_Inc(bank)); IF (DQML_nwv = '0') THEN MemData(Bank)(Location) := -1; IF Violation = '0' THEN MemData(Bank)(Location) := to_nat(DataIn(7 downto 0)); END IF; END IF; IF (DQMH_nwv = '0') THEN MemData(Bank)(Location+1) := -1; IF Violation = '0' THEN MemData(Bank)(Location+1) := to_nat(DataIn(15 downto 8)); END IF; END IF; Burst_Cnt(bank) := Burst_Cnt(bank) + 1; wrt_in <= '1'; END IF; ELSIF cur_bank = bank THEN ASSERT false REPORT InstancePath & partID & ": Illegal command" & " received in write state." SEVERITY SeverityMode; END IF; WHEN read => IF (command = bst) THEN statebank(bank) <= bank_act; Burst_Cnt(bank) := 0; ELSIF (command = read) THEN IF cur_bank = bank THEN MemAddr(bank)(9 downto 0) := (others => '0'); -- clr old addr MemAddr(bank)(9 downto Burst_Bits) := AddressIn(9 downto Burst_Bits); --latch col addr IF (Burst_Bits > 0) THEN Burst_Inc(bank) := to_nat(AddressIn(Burst_Bits-1 downto 0)); END IF; StartAddr(bank) := Burst_Inc(bank) mod 8; BaseLoc(bank) := to_nat(MemAddr(bank)); Location := 2*(BaseLoc(bank) + Burst_Inc(bank)); DataDrive(7 downto 0) := (others => 'U'); IF MemData(Bank)(Location) > -2 THEN DataDrive(7 downto 0) := (others => 'X'); END IF; IF MemData(Bank)(Location) > -1 THEN DataDrive(7 downto 0) := to_slv(MemData(Bank)(Location),8); END IF; DataDrive(15 downto 8) := (others => 'U'); IF MemData(Bank)(Location+1) > -2 THEN DataDrive(15 downto 8) := (others => 'X'); END IF; IF MemData(Bank)(Location+1) > -1 THEN DataDrive(15 downto 8) := to_slv(MemData(Bank)(Location+1),8); END IF; Burst_Cnt(bank) := 1; IF (AddressIn(10) = '0') THEN statebank(bank) <= read; ELSIF (AddressIn(10) = '1') THEN statebank(bank) <= read_auto_pre; END IF; ELSE statebank(bank) <= bank_act; END IF; ELSIF (command = writ) THEN IF cur_bank = bank THEN ASSERT rcdt_out(bank) = '0' REPORT InstancePath & partID & BankString & ": write command" & " received too soon after active." SEVERITY SeverityMode; ASSERT ((AddressIn(10) = '0') OR (AddressIn(10) = '1')) REPORT InstancePath & partID & BankString & ": AddressIn(10) = X" & " during write command. Next state unknown." SEVERITY SeverityMode; MemAddr(bank)(9 downto 0) := (others => '0'); -- clr old addr MemAddr(bank)(9 downto Burst_Bits) := AddressIn(9 downto Burst_Bits); --latch col addr IF (Burst_Bits > 0) THEN Burst_Inc(bank) := to_nat(AddressIn(Burst_Bits-1 downto 0)); END IF; StartAddr(bank) := Burst_Inc(bank) mod 8; BaseLoc(bank) := to_nat(MemAddr(bank)); Location := 2*(BaseLoc(bank) + Burst_Inc(bank)); IF (DQML_nwv = '0') THEN MemData(Bank)(Location) := -1; IF Violation = '0' THEN MemData(Bank)(Location) := to_nat(DataIn(7 downto 0)); END IF; END IF; IF (DQMH_nwv = '0') THEN MemData(Bank)(Location+1) := -1; IF Violation = '0' THEN MemData(Bank)(Location+1) := ⌨️ 快捷键说明
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