📄 cy7c131.ftm

📁 vhdl cod for ram.For sp3e
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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for cy7c131 Parts</TITLE><BODY><REVISION.HISTORY>version: |  author:  | mod date: | changes made:  V1.0    R. Munden    00 Apr 24   Initial release  V1.1    R. Munden    08 MAY 23   Corrected IOL port name</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>cy7c131<FMFTIME><FMFTIME>CY7C131-15JC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE>CY7C131-15NC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE><COMMENT>The values listed are for VCC=4.5 to 5.5V, CL=50pF, Ta=0 to 70C</COMMENT><COMMENT>Datasheet gives Min. OR Max. values for each delay. Other values are derived.</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH RWL INTRNeg (5:10:15) (5:10:15))    (IOPATH OELNeg IOL0 () () (3:6:10) (3:6:10) (3:6:10) (3:6:10))    (IOPATH CELNeg IOL0 () () (3:6:10) (3:10:15) (3:6:10) (3:10:15))    (IOPATH AL0 INTLNeg (5:10:15) (5:10:15))    (IOPATH AL0 IOL0 (0:8:15) (0:8:15))    (IOPATH AL0 BUSYLNeg (5:10:15) (5:10:15))    (IOPATH CELNeg BUSYLNeg (5:10:15) (5:10:15))  ))  (TIMINGCHECK    (SETUP AL0 CELNeg (0:0:0))    (SETUP AL0 RWL (0:0:0))    (SETUP AL1 RWL (12:12:12))    (SETUP CELNeg RWL (12:12:12))    (SETUP IOL0 RWL (10:10:10))    (HOLD AL0 CELNeg (0:0:0))    (WIDTH (negedge RWL) (12:12:12))  )</TIMING></FMFTIME><FMFTIME>CY7C131-25JC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE>CY7C131-25NC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE><COMMENT>The values listed are for VCC=4.5 to 5.5V, CL=50pF, Ta=0 to 70C</COMMENT><COMMENT>Datasheet gives Min. OR Max. values for each delay. Other values are derived.</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH RWL INTRNeg (8:17:25) (8:17:25))    (IOPATH OELNeg IOL0 () () (5:10:15) (3:10:15) (5:10:15) (3:10:15))    (IOPATH CELNeg IOL0 () () (5:10:15) (5:15:25) (5:10:15) (5:15:25))    (IOPATH AL0 INTLNeg (8:17:25) (8:17:25))    (IOPATH AL0 IOL0 (8:17:25) (8:17:25))    (IOPATH AL0 BUSYLNeg (7:14:20) (7:14:20))    (IOPATH CELNeg BUSYLNeg (7:14:20) (7:14:20))  ))  (TIMINGCHECK    (SETUP AL0 CELNeg (0:0:0))    (SETUP AL0 RWL (0:0:0))    (SETUP AL1 RWL (20:20:20))    (SETUP CELNeg RWL (20:20:20))    (SETUP IOL0 RWL (15:15:15))    (HOLD AL0 CELNeg (2:2:2))    (WIDTH (negedge RWL) (15:15:15))  )</TIMING></FMFTIME><FMFTIME>CY7C131-30JC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE>CY7C131-30NC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE><COMMENT>The values listed are for VCC=4.5 to 5.5V, CL=50pF, Ta=0 to 70C</COMMENT><COMMENT>Datasheet gives Min. OR Max. values for each delay. Other values are derived.</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH RWL INTRNeg (8:17:25) (8:17:25))    (IOPATH OELNeg IOL0 () () (5:10:15) (3:10:20) (5:10:15) (3:10:20.))    (IOPATH CELNeg IOL0 () () (5:10:15) (5:15:30) (5:10:15) (5:15:30))    (IOPATH AL0 INTLNeg (8:17:25) (8:17:25))    (IOPATH AL0 IOL0 (10:20:30) (10:20:30))    (IOPATH AL0 BUSYLNeg (7:15:20) (7:15:20))    (IOPATH CELNeg BUSYLNeg (7:15:20) (7:15:20))  ))  (TIMINGCHECK    (SETUP AL0 CELNeg (0:0:0))    (SETUP AL0 RWL (0:0:0))    (SETUP AL1 RWL (25:25:25))    (SETUP CELNeg RWL (25:25:25))    (SETUP IOL0 RWL (15:15:15))    (HOLD AL0 CELNeg (2:2:2))    (WIDTH (negedge RWL) (25:25:25))  )</TIMING></FMFTIME><FMFTIME>CY7C131-35JC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE>CY7C131-35NC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE><COMMENT>The values listed are for VCC=4.5 to 5.5V, CL=50pF, Ta=0 to 70C</COMMENT><COMMENT>Datasheet gives Min. OR Max. values for each delay. Other values are derived.</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH RWL INTRNeg (8:16:25) (8:16:25))    (IOPATH OELNeg IOL0 () () (7:14:20) (3:14:20) (7:14:20) (3:14:20))    (IOPATH CELNeg IOL0 () () (7:14:20) (5:25:35) (7:14:20) (5:25:35))    (IOPATH AL0 INTLNeg (7:14:20) (7:14:20))    (IOPATH AL0 IOL0 (12:24:35) (12:24:35))    (IOPATH AL0 BUSYLNeg (7:14:20) (7:14:20))    (IOPATH CELNeg BUSYLNeg (7:14:20) (7:14:20))  ))  (TIMINGCHECK    (SETUP AL0 CELNeg (0))    (SETUP AL0 RWL (0))    (SETUP AL1 RWL (30:30:30))    (SETUP CELNeg RWL (30:30:30))    (SETUP IOL0 RWL (15:15:15))    (HOLD AL0 CELNeg (2:2:2))    (WIDTH (negedge RWL) (25:25:25))  )</TIMING></FMFTIME><FMFTIME>CY7C131-45JC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE>CY7C131-45NC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE><COMMENT>The values listed are for VCC=4.5 to 5.5V, CL=50pF, Ta=0 to 70C</COMMENT><COMMENT>Datasheet gives Min. OR Max. values for each delay. Other values are derived.</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH RWL INTRNeg (12:24:35) (12:24:35))    (IOPATH OELNeg IOL0 () () (7:14:20) (3:15:25) (7:14:20) (3:15:25))    (IOPATH CELNeg IOL0 () () (7:14:20) (5:35:45) (7:14:20) (5:35:45))    (IOPATH AL0 INTLNeg (12:24:35) (12:24:35))    (IOPATH AL0 IOL0 (15:30:45) (15:30:45))    (IOPATH AL0 BUSYLNeg (8:16:25) (8:16:25))    (IOPATH CELNeg BUSYLNeg (8:16:25) (8:16:25))  ))  (TIMINGCHECK    (SETUP AL0 CELNeg (0:0:0))    (SETUP AL0 RWL (0:0:0))    (SETUP AL1 RWL (35:35:35))    (SETUP CELNeg RWL (35:35:35))    (SETUP IOL0 RWL (20:20:20))    (HOLD AL0 CELNeg (2:2:2))    (WIDTH (negedge RWL) (30:30:30))  )</TIMING></FMFTIME><FMFTIME>CY7C131-55JC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE>CY7C131-55NC<SOURCE>Cypress Semiconductor datasheet Revised March 27, 1997</SOURCE><COMMENT>The values listed are for VCC=4.5 to 5.5V, CL=50pF, Ta=0 to 70C</COMMENT><COMMENT>Datasheet gives Min. OR Max. values for each delay. Other values are derived.</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH RWL INTRNeg (15:30:45) (15:30:45))    (IOPATH OELNeg IOL0 () () (8:17:25) (3:17:25) (8:17:25) (3:17:25))    (IOPATH CELNeg IOL0 () () (8:17:25) (5:40:55) (8:17:25) (5:40:55))    (IOPATH AL0 INTLNeg (15:30:45) (15:30:45))    (IOPATH AL0 IOL0 (20:40:55) (20:40:55))    (IOPATH AL0 BUSYLNeg (10:20:30) (10:20:30))    (IOPATH CELNeg BUSYLNeg (10:20:30) (10:20:30))  ))  (TIMINGCHECK    (SETUP AL0 CELNeg (0:0:0))    (SETUP AL0 RWL (0:0:0))    (SETUP AL1 RWL (40:40:40))    (SETUP CELNeg RWL (40:40:40))    (SETUP IOL0 RWL (20:20:20))    (HOLD AL0 CELNeg (2:2:2))    (WIDTH (negedge RWL) (30:30:30))  )</TIMING></FMFTIME><FMFTIME>IDT7130LA20J<SOURCE>Integrated Device Technology DSC-2689/9 August 1999</SOURCE>IDT7130LA20PT<SOURCE>Integrated Device Technology DSC-2689/9 August 1999</SOURCE>IDT7130LA20TF<SOURCE>Integrated Device Technology DSC-2689/9 August 1999</SOURCE>IDT7130SA20J<SOURCE>Integrated Device Technology DSC-2689/9 August 1999</SOURCE>IDT7130SA20PT<SOURCE>Integrated Device Technology DSC-2689/9 August 1999</SOURCE>IDT7130SA20TF<SOURCE>Integrated Device Technology DSC-2689/9 August 1999</SOURCE><COMMENT>The values listed are for VCC=4.5 to 5.5V, CL=50pF, Ta=0 to 70C</COMMENT><COMMENT>Datasheet gives Min. OR Max. values for each delay. Other values are derived.</COMMENT>
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