📄 cy7c1380.ftm

📁 vhdl cod for ram.For sp3e
💻 FTM
字号:
<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for cy7c1380 Parts</TITLE><BODY><REVISION.HISTORY>version: |  author:  | mod date: | changes made:  V1.0    R. Munden    03 Aug 30   Initial release</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>cy7c1380<FMFTIME>CY7C1380C-133AC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE><COMMENT>The values listed are for VCC=3.125V to 3.6V, CL=30pF, Ta=-40 to +85 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.4:2.8:4.2) (1.4:2.8:4.2) (1.1:2.3:3.4) (1.3:2.6:3.9) (1.1:2.3:3.4) (1.3:2.6:3.9))    (IOPATH OENeg DQA0 () () (1.3:2.7:4.0) (0:2.1:4.2) (1.3:2.7:4.0) (0:2.1:4.2))  ))  (TIMINGCHECK    (SETUP A0 CLK (1.5:1.5:1.5))     (SETUP DQA0 CLK (1.5:1.5:1.5))     (SETUP ADVNeg CLK (1.5:1.5:1.5))     (SETUP ADSCNeg CLK (1.5:1.5:1.5))     (SETUP CE2 CLK (1.5:1.5:1.5))     (SETUP BWANeg CLK (1.5:1.5:1.5))     (HOLD A0 CLK (.5:.5:.5))     (HOLD DQA0 CLK (.5:.5:.5))     (HOLD ADVNeg CLK (.5:.5:.5))     (HOLD ADSCNeg CLK (.5:.5:.5))     (HOLD CE2 CLK (.5:.5:.5))     (HOLD BWANeg CLK (.5:.5:.5))     (HOLD ADSCNeg ZZ (.5:.5:.5))     (WIDTH (posedge CLK) (2.5:2.5:2.5))     (WIDTH (negedge CLK) (2.5:2.5:2.5))     (PERIOD (posedge CLK) (7.5:7.5:7.5))   )</TIMING></FMFTIME><FMFTIME>CY7C1380C-167AC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE>CY7C1380C-167BGC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE>CY7C1380C-167BZC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE><COMMENT>The values listed are for VCC=3.125V to 3.6V, CL=30pF, Ta=-40 to +85 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.1:2.3:3.4) (1.1:2.3:3.4) (1.1:2.3:3.4) (1.3:2.6:3.9) (1.1:2.3:3.4) (1.3:2.6:3.9))    (IOPATH OENeg DQA0 () () (1.1:2.3:3.4) (0:2.3:3.4) (1.1:2.3:3.4) (0:2.3:3.4))  ))  (TIMINGCHECK    (SETUP A0 CLK (1.5:1.5:1.5))     (SETUP DQA0 CLK (1.5:1.5:1.5))     (SETUP ADVNeg CLK (1.5:1.5:1.5))     (SETUP ADSCNeg CLK (1.5:1.5:1.5))     (SETUP CE2 CLK (1.5:1.5:1.5))     (SETUP BWANeg CLK (1.5:1.5:1.5))     (HOLD A0 CLK (.5:.5:.5))     (HOLD DQA0 CLK (.5:.5:.5))     (HOLD ADVNeg CLK (.5:.5:.5))     (HOLD ADSCNeg CLK (.5:.5:.5))     (HOLD CE2 CLK (.5:.5:.5))     (HOLD BWANeg CLK (.5:.5:.5))     (HOLD ADSCNeg ZZ (.5:.5:.5))     (WIDTH (posedge CLK) (2.2:2.2:2.2))     (WIDTH (negedge CLK) (2.2:2.2:2.2))     (PERIOD (posedge CLK) (6.0:6.0:6.0))   )</TIMING></FMFTIME><FMFTIME>CY7C1380C-200AC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE>CY7C1380C-200BGC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE>CY7C1380C-200BZC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE><COMMENT>The values listed are for VCC=3.125V to 3.6V, CL=30pF, Ta=-40 to +85 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.0:2.0:3.0) (1.0:2.0:3.0) (1.0:2.0:3.0) (1.3:2.6:3.9) (1.0:2.0:3.0) (1.3:2.6:3.9))    (IOPATH OENeg DQA0 () () (1.0:2.0:3.0) (0:2.0:3.0) (1.0:2.0:3.0) (0:2.0:3.0))  ))  (TIMINGCHECK    (SETUP A0 CLK (1.4:1.4:1.4))     (SETUP DQA0 CLK (1.4:1.4:1.4))     (SETUP ADVNeg CLK (1.4:1.4:1.4))     (SETUP ADSCNeg CLK (1.4:1.4:1.4))     (SETUP CE2 CLK (1.4:1.4:1.4))     (SETUP BWANeg CLK (1.4:1.4:1.4))     (HOLD A0 CLK (.4:.4:.4))     (HOLD DQA0 CLK (.4:.4:.4))     (HOLD ADVNeg CLK (.4:.4:.4))     (HOLD ADSCNeg CLK (.4:.4:.4))     (HOLD CE2 CLK (.4:.4:.4))     (HOLD BWANeg CLK (.4:.4:.4))     (HOLD ADSCNeg ZZ (.4:.4:.4))     (WIDTH (posedge CLK) (2.0:2.0:2.0))     (WIDTH (negedge CLK) (2.0:2.0:2.0))     (PERIOD (posedge CLK) (5.0:5.0:5.0))   )</TIMING></FMFTIME><FMFTIME>CY7C1380C-225AC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE>CY7C1380C-225BGC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE>CY7C1380C-225BZC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE><COMMENT>The values listed are for VCC=3.125V to 3.6V, CL=30pF, Ta=-40 to +85 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (0.9:1.9:2.8) (0.9:1.9:2.8) (0.9:1.9:2.8) (1:2:3) (0.9:1.9:2.8) (1:2:3))    (IOPATH OENeg DQA0 () () (0.9:1.9:2.8) (0:1.9:2.8) (0.9:1.9:2.8) (0:1.9:2.8))  ))  (TIMINGCHECK    (SETUP A0 CLK (1.4:1.4:1.4))     (SETUP DQA0 CLK (1.4:1.4:1.4))     (SETUP ADVNeg CLK (1.4:1.4:1.4))     (SETUP ADSCNeg CLK (1.4:1.4:1.4))     (SETUP CE2 CLK (1.4:1.4:1.4))     (SETUP BWANeg CLK (1.4:1.4:1.4))     (HOLD A0 CLK (0.4:0.4:0.4))     (HOLD DQA0 CLK (0.4:0.4:0.4))     (HOLD ADVNeg CLK (0.4:0.4:0.4))     (HOLD ADSCNeg CLK (0.4:0.4:0.4))     (HOLD CE2 CLK (0.4:0.4:0.4))     (HOLD BWANeg CLK (0.4:0.4:0.4))     (HOLD ADSCNeg ZZ (0.4:0.4:0.4))     (WIDTH (posedge CLK) (2.0:2.0:2.0))     (WIDTH (negedge CLK) (2.0:2.0:2.0))     (PERIOD (posedge CLK) (4.4:4.4:4.4))   )</TIMING></FMFTIME><FMFTIME>CY7C1380C-250AC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE>CY7C1380C-250BGC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE>CY7C1380C-250BZC<SOURCE>Cypress 38-05237 Rev. B, December 18, 2002</SOURCE><COMMENT>The values listed are for VCC=3.125V to 3.6V, CL=30pF, Ta=-40 to +85 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (0.7:1.4:2.6) (0.7:1.4:2.6) (0.7:1.4:2.6) (1:2:3) (0.7:1.4:2.6) (1:2:3))    (IOPATH OENeg DQA0 () () (0.7:1.4:2.6) (0:1.4:2.6) (0.7:1.4:2.6) (0:1.4:2.6))  ))  (TIMINGCHECK    (SETUP A0 CLK (1.2:1.2:1.2))     (SETUP DQA0 CLK (1.2:1.2:1.2))     (SETUP ADVNeg CLK (1.2:1.2:1.2))     (SETUP ADSCNeg CLK (1.2:1.2:1.2))     (SETUP CE2 CLK (1.2:1.2:1.2))     (SETUP BWANeg CLK (1.2:1.2:1.2))     (HOLD A0 CLK (0.3:0.3:0.3))     (HOLD DQA0 CLK (0.3:0.3:0.3))     (HOLD ADVNeg CLK (0.3:0.3:0.3))     (HOLD ADSCNeg CLK (0.3:0.3:0.3))     (HOLD CE2 CLK (0.3:0.3:0.3))     (HOLD BWANeg CLK (0.3:0.3:0.3))     (HOLD ADSCNeg ZZ (0.3:0.3:0.3))     (WIDTH (posedge CLK) (1.7:1.7:1.7))     (WIDTH (negedge CLK) (1.7:1.7:1.7))     (PERIOD (posedge CLK) (4.0:4.0:4.0))   )</TIMING></FMFTIME><FMFTIME>K7A163600A-FC14<SOURCE>Samsung datasheet Rev 2.1 April 2003</SOURCE>K7A163600A-QC14<SOURCE>Samsung datasheet Rev 2.1 April 2003</SOURCE><COMMENT>The values listed are for VCC=3.165V to 3.465V, CL=30pF, Ta=0 to +70 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.3:2.7:4.0) (1.3:2.7:4.0) (1.5:2.5:3.5) (0:2.7:4.0) (1.5:2.5:3.5) (0:2.7:4.0))    (IOPATH OENeg DQA0 () () (1.5:2.5:3.5) (0:2.7:4.0) (1.5:2.5:3.5) (0:2.7:4.0))  ))  (TIMINGCHECK    (SETUP A0 CLK (1.5:1.5:1.5))     (SETUP DQA0 CLK (1.5:1.5:1.5))     (SETUP ADVNeg CLK (1.5:1.5:1.5))     (SETUP ADSCNeg CLK (1.5:1.5:1.5))     (SETUP CE2 CLK (1.5:1.5:1.5))     (SETUP BWANeg CLK (1.5:1.5:1.5))     (HOLD A0 CLK (0.5:0.5:0.5))     (HOLD DQA0 CLK (0.5:0.5:0.5))     (HOLD ADVNeg CLK (0.5:0.5:0.5))     (HOLD ADSCNeg CLK (0.5:0.5:0.5))     (HOLD CE2 CLK (0.5:0.5:0.5))     (HOLD BWANeg CLK (0.5:0.5:0.5))     (HOLD ADSCNeg ZZ (0.5:0.5:0.5))     (WIDTH (posedge CLK) (2.5:2.5:2.5))     (WIDTH (negedge CLK) (2.5:2.5:2.5))     (PERIOD (posedge CLK) (7.2:7.2:7.2))   )</TIMING></FMFTIME><FMFTIME>K7A163600A-FC16<SOURCE>Samsung datasheet Rev 2.1 April 2003</SOURCE>K7A163600A-HC16<SOURCE>Samsung datasheet Rev 2.1 April 2003</SOURCE>K7A163600A-QC16<SOURCE>Samsung datasheet Rev 2.1 April 2003</SOURCE><COMMENT>The values listed are for VCC=3.165V to 3.465V, CL=30pF, Ta=0 to +70 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.2:2.6:3.5) (1.2:2.6:3.5) (1.5:2.3:3.0) (0:2.6:3.5) (1.5:2.3:3.0) (0:2.6:3.5))    (IOPATH OENeg DQA0 () () (1:2:3) (0:2.6:3.5) (1:2:3) (0:2.6:3.5))  ))  (TIMINGCHECK    (SETUP A0 CLK (1.5:1.5:1.5))     (SETUP DQA0 CLK (1.5:1.5:1.5))     (SETUP ADVNeg CLK (1.5:1.5:1.5))     (SETUP ADSCNeg CLK (1.5:1.5:1.5))     (SETUP CE2 CLK (1.5:1.5:1.5))     (SETUP BWANeg CLK (1.5:1.5:1.5))     (HOLD A0 CLK (0.5:0.5:0.5))     (HOLD DQA0 CLK (0.5:0.5:0.5))     (HOLD ADVNeg CLK (0.5:0.5:0.5))     (HOLD ADSCNeg CLK (0.5:0.5:0.5))     (HOLD CE2 CLK (0.5:0.5:0.5))     (HOLD BWANeg CLK (0.5:0.5:0.5))     (HOLD ADSCNeg ZZ (0.5:0.5:0.5))     (WIDTH (posedge CLK) (2.1:2.1:2.1))     (WIDTH (negedge CLK) (2.1:2.1:2.1))     (PERIOD (posedge CLK) (6.0:6.0:6.0))   )</TIMING></FMFTIME><FMFTIME>K7A163600A-FC20<SOURCE>Samsung datasheet Rev 2.1 April 2003</SOURCE>K7A163600A-QC20<SOURCE>Samsung datasheet Rev 2.1 April 2003</SOURCE><COMMENT>The values listed are for VCC=3.165V to 3.465V, CL=30pF, Ta=0 to +70 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (1.0:2.1:3.1) (1.0:2.1:3.1) (1.5:2.3:3.0) (0:2.1:3.1) (1.5:2.3:3.0) (0:2.1:3.1))    (IOPATH OENeg DQA0 () () (1:2:3) (0:2.1:3.1) (1:2:3) (0:2.1:3.1))  ))  (TIMINGCHECK    (SETUP A0 CLK (1.4:1.4:1.4))     (SETUP DQA0 CLK (1.4:1.4:1.4))     (SETUP ADVNeg CLK (1.4:1.4:1.4))     (SETUP ADSCNeg CLK (1.4:1.4:1.4))     (SETUP CE2 CLK (1.4:1.4:1.4))     (SETUP BWANeg CLK (1.4:1.4:1.4))     (HOLD A0 CLK (0.4:0.4:0.4))     (HOLD DQA0 CLK (0.4:0.4:0.4))     (HOLD ADVNeg CLK (0.4:0.4:0.4))     (HOLD ADSCNeg CLK (0.4:0.4:0.4))     (HOLD CE2 CLK (0.4:0.4:0.4))     (HOLD BWANeg CLK (0.4:0.4:0.4))     (HOLD ADSCNeg ZZ (0.4:0.4:0.4))     (WIDTH (posedge CLK) (2.0:2.0:2.0))     (WIDTH (negedge CLK) (2.0:2.0:2.0))     (PERIOD (posedge CLK) (5.0:5.0:5.0))   )</TIMING></FMFTIME><FMFTIME>K7A163600A-FC22<SOURCE>Samsung datasheet Rev 2.1 April 2003</SOURCE>K7A163600A-QC22<SOURCE>Samsung datasheet Rev 2.1 April 2003</SOURCE><COMMENT>The values listed are for VCC=3.165V to 3.465V, CL=30pF, Ta=0 to +70 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (0.7:1.5:2.8) (0.7:1.5:2.8) (1.5:2.2:2.8) (0:1.5:2.8) (1.5:2.2:2.8) (0:1.5:2.8))    (IOPATH OENeg DQA0 () () (0.7:2.2:2.8) (0:1.5:2.8) (0.7:2.2:2.8) (0:1.5:2.8))  ))  (TIMINGCHECK    (SETUP A0 CLK (1.4:1.4:1.4))     (SETUP DQA0 CLK (1.4:1.4:1.4))     (SETUP ADVNeg CLK (1.4:1.4:1.4))     (SETUP ADSCNeg CLK (1.4:1.4:1.4))     (SETUP CE2 CLK (1.4:1.4:1.4))     (SETUP BWANeg CLK (1.4:1.4:1.4))     (HOLD A0 CLK (0.4:0.4:0.4))     (HOLD DQA0 CLK (0.4:0.4:0.4))     (HOLD ADVNeg CLK (0.4:0.4:0.4))     (HOLD ADSCNeg CLK (0.4:0.4:0.4))     (HOLD CE2 CLK (0.4:0.4:0.4))     (HOLD BWANeg CLK (0.4:0.4:0.4))     (HOLD ADSCNeg ZZ (0.4:0.4:0.4))     (WIDTH (posedge CLK) (1.8:1.8:1.8))     (WIDTH (negedge CLK) (1.8:1.8:1.8))     (PERIOD (posedge CLK) (4.4:4.4:4.4))   )</TIMING></FMFTIME><FMFTIME>K7A163600A-FC25<SOURCE>Samsung datasheet Rev 2.1 April 2003</SOURCE>K7A163600A-QC25<SOURCE>Samsung datasheet Rev 2.1 April 2003</SOURCE><COMMENT>The values listed are for VCC=3.165V to 3.465V, CL=30pF, Ta=0 to +70 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (0.9:1.7:2.6) (0.8:1.7:2.6) (1.5:2.1:2.6) (0:1.7:2.6) (1.5:2.1:2.6) (0:1.7:2.6))    (IOPATH OENeg DQA0 () () (0.9:1.7:2.6) (0:1.7:2.6) (0.9:1.7:2.6) (0:1.7:2.6))  ))  (TIMINGCHECK    (SETUP A0 CLK (1.2:1.2:1.2))     (SETUP DQA0 CLK (1.2:1.2:1.2))     (SETUP ADVNeg CLK (1.2:1.2:1.2))     (SETUP ADSCNeg CLK (1.2:1.2:1.2))     (SETUP CE2 CLK (1.2:1.2:1.2))     (SETUP BWANeg CLK (1.2:1.2:1.2))     (HOLD A0 CLK (0.3:0.3:0.3))     (HOLD DQA0 CLK (0.3:0.3:0.3))     (HOLD ADVNeg CLK (0.3:0.3:0.3))     (HOLD ADSCNeg CLK (0.3:0.3:0.3))     (HOLD CE2 CLK (0.3:0.3:0.3))     (HOLD BWANeg CLK (0.3:0.3:0.3))     (HOLD ADSCNeg ZZ (0.3:0.3:0.3))     (WIDTH (posedge CLK) (1.7:1.7:1.7))     (WIDTH (negedge CLK) (1.7:1.7:1.7))     (PERIOD (posedge CLK) (4.0:4.0:4.0))   )</TIMING></FMFTIME></BODY></FTML>
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -