k7r320982m.vhd

vhdl cod for ram.For sp3e

        SIGNAL CTRIG    : std_ulogic;
        SIGNAL KCTRIG   : std_ulogic;
        SIGNAL KCTRIGN  : std_ulogic;
        SIGNAL CPERIOD  : time := 4 ns;       -- C period
        SIGNAL KPERIOD  : time := 4 ns;
        SIGNAL CInt     : std_ulogic := '0';
        SIGNAL CNegInt  : std_ulogic := '0';
        SIGNAL Ktemp    : std_ulogic := '0';
        SIGNAL Ctemp    : std_ulogic := '0';
        SIGNAL KInt     : std_ulogic := '0';
        SIGNAL KNegInt  : std_ulogic := '0';

        SIGNAL CHalfPer : time := 4 ps;
        SIGNAL Cdlldelay: time := 0 ns;
        SIGNAL KHalfPer : time := 4 ps;
        SIGNAL Kdlldelay: time := 0 ns;
        TYPE cmode IS (c, k);
        SIGNAL mode     : cmode := c;

    BEGIN
        ----------------------------------------------
        -- DLL model functional section            ---
        ----------------------------------------------
        C_DLL: PROCESS(CIn, Ctemp)

        VARIABLE CIn_period    : Time := 1 ms;
        VARIABLE prev_CIn      : Time := 0 ns;
        VARIABLE Ctemp_period  : Time := 0 ns;
        VARIABLE Ctemp_period1 : Time := 0 ns;
        VARIABLE Ctemp_period2 : Time := 0 ns;
        VARIABLE prev_Ctemp    : Time := 0 ns;
        VARIABLE dll_lock      : BOOLEAN := false;
        VARIABLE toggle1       : boolean;
        VARIABLE toggle2       : boolean;
        VARIABLE DllDisable    : BOOLEAN := false;  -- Disable dll mode

        BEGIN
            DllDisable :=(DLLNeg_ipd = '0');
        IF mode = c THEN
            IF rising_edge(CIn) THEN
                CIn_period := NOW - prev_CIn;
                prev_CIn := NOW;
                IF CIn_period > 30 ns THEN
                    dll_lock := false;
                    ASSERT false
                        REPORT "C mode DLL reseting"
                        SEVERITY note;
                END IF;
            END IF;

            IF rising_edge(Ctemp) THEN
                Ctemp_period := NOW - prev_Ctemp;
                prev_Ctemp := NOW;
                IF toggle1 AND toggle2 AND not(dll_lock) AND NOT
                DllDisable THEN
                    IF Ctemp_period > CIn_period THEN
                        Chalfper <= Chalfper - 51 ps;
                        dll_lock := false;
                    ELSIF Ctemp_period < CIn_period THEN
                        Chalfper <= Chalfper + 4 ps;
                        dll_lock := false;
                    ELSIF Ctemp_period = Ctemp_period2 THEN -- stable?
                        dll_lock := true;
                        ASSERT false
                            REPORT "C mode DLL lock achieved"
                            SEVERITY note;
                    ELSE
                        Ctemp_period2 := Ctemp_period1;
                        Ctemp_period1 := Ctemp_period;
                    END IF;
                END IF;
                toggle1 := not toggle1;
                IF toggle1 THEN
                    toggle2 := not toggle2;
                ELSE
                    Cdlldelay <= 0 ps;
                END IF;
            END IF;

            IF rising_edge(Ctemp) AND dll_lock AND toggle1 AND toggle2 THEN
                IF (prev_CIn + tpd_C_Q1) < NOW THEN
                    IF Cdlldelay < CIn_period THEN
                        Cdlldelay <= Cdlldelay - 60 ps;
                    END IF;
                END IF;
            END IF;
        END IF;

        END PROCESS C_DLL;

        C_temp : PROCESS(Ctemp,DLLNeg_ipd) -- generating internal clock from DLL
        BEGIN
            IF NOT DLLNeg_ipd = '0' THEN
                Ctemp <= not(Ctemp) AFTER CHalfPer + Cdlldelay;
            END IF;
        END PROCESS C_temp;

        K_DLL: PROCESS(KIn, Ktemp)

        VARIABLE KIn_period   : Time := 1 ms;
        VARIABLE prev_KIn     : Time := 0 ns;
        VARIABLE Ktemp_period : Time := 0 ns;
        VARIABLE Ktemp_period1 : Time := 0 ns;
        VARIABLE Ktemp_period2 : Time := 0 ns;
        VARIABLE prev_Ktemp   : Time := 0 ns;
        VARIABLE dll_lock     : BOOLEAN := false;
        VARIABLE toggle1      : boolean;
        VARIABLE toggle2      : boolean;
        VARIABLE DllDisable   : BOOLEAN := false;  -- Disable dll mode

        BEGIN
            DllDisable :=(DLLNeg_ipd = '0');
        IF mode = k THEN
            IF rising_edge(KIn) THEN
                KIn_period := NOW - prev_KIn;
                prev_KIn := NOW;
                IF KIn_period > 30 ns THEN
                    dll_lock := false;
                    ASSERT false
                        REPORT "K mode DLL reseting"
                        SEVERITY note;
                END IF;
            END IF;

            IF rising_edge(Ktemp) THEN
                Ktemp_period := NOW - prev_Ktemp;
                prev_Ktemp := NOW;
                IF toggle1 AND toggle2 AND not(dll_lock)AND NOT
                    DllDisable THEN
                    IF Ktemp_period > KIn_period THEN
                        Khalfper <= Khalfper - 51 ps;
                        dll_lock := false;
                    ELSIF Ktemp_period < KIn_period THEN
                        Khalfper <= Khalfper + 4 ps;
                        dll_lock := false;
                    ELSIF Ktemp_period = Ktemp_period2 THEN -- stable?
                        dll_lock := true;
                        ASSERT false
                            REPORT "K mode DLL lock achieved"
                            SEVERITY note;
                    ELSE
                        Ktemp_period2 := Ktemp_period1;
                        Ktemp_period1 := Ktemp_period;
                    END IF;
                END IF;
                toggle1 := not toggle1;
                IF toggle1 THEN
                    toggle2 := not toggle2;
                ELSE
                    Kdlldelay <= 0 ps;
                END IF;
            END IF;

            IF rising_edge(Ktemp) AND dll_lock AND toggle1 AND toggle2 THEN
                IF (prev_KIn + tpd_C_Q1) < NOW THEN
                    IF Kdlldelay < KIn_period THEN
                        Kdlldelay <= Kdlldelay - 60 ps;
                    END IF;
                END IF;
            END IF;
        END IF;

        END PROCESS K_DLL;

        K_temp : PROCESS(Ktemp,DLLNeg_ipd) -- generating internal clock from DLL
        BEGIN
            IF NOT DLLNeg_ipd = '0' THEN
                Ktemp <= not(Ktemp)  AFTER KHalfPer + Kdlldelay;
            END IF;
        END PROCESS K_temp;

        C_int : PROCESS (CIn, Ctemp, KIn, Ktemp)-- Passing clock based on DLL_EN
        BEGIN
            IF (not DLLNegIn= '0') THEN
                IF mode = c THEN
                    CInt <= TRANSPORT Ctemp;
                    CNegInt <= TRANSPORT not Ctemp;
                ELSIF mode = k THEN
                    CInt <= TRANSPORT Ktemp;
                    CNegInt <= TRANSPORT not Ktemp;
                END IF;
            ELSE
                IF mode = c THEN
                    CInt <= CIn ;
                    CNegInt <= CNegIn ;
                ELSIF mode = k THEN
                    CInt <= KIn ;
                    CNegInt <= KNegIn ;
                END IF;
            END IF;
        END PROCESS C_int;

        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Behavior : PROCESS (BWNIn, CInt, CNegInt, KIn,
                            KNegIn, RInt, WInt, AddressIn, Dat0In,
                            KTRIG, CTRIG, KCTRIG, KCTRIGN)

            -- Timing Check Variables
            VARIABLE Tviol_A0_K         : X01 := '0';
            VARIABLE TD_A0_K            : VitalTimingDataType;

            VARIABLE Tviol_A0_KNeg      : X01 := '0';
            VARIABLE TD_A0_KNeg         : VitalTimingDataType;

            VARIABLE Tviol_D0_K         : X01 := '0';
            VARIABLE TD_D0_K            : VitalTimingDataType;

            VARIABLE Tviol_D0_KNeg      : X01 := '0';
            VARIABLE TD_D0_KNeg         : VitalTimingDataType;

            VARIABLE Tviol_RNeg_K       : X01 := '0';
            VARIABLE TD_RNeg_K          : VitalTimingDataType;

            VARIABLE Tviol_WNeg_K       : X01 := '0';
            VARIABLE TD_WNeg_K          : VitalTimingDataType;

            VARIABLE Tviol_BWNeg_K     : X01 := '0';
            VARIABLE TD_BWNeg_K        : VitalTimingDataType;

            VARIABLE Tviol_BWNeg_KNeg  : X01 := '0';
            VARIABLE TD_BWNeg_KNeg     : VitalTimingDataType;

            VARIABLE Pviol_C            :  X01 := '0';
            VARIABLE TD_C          : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_CNeg         :  X01 := '0';
            VARIABLE TD_CNeg       : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_K            :  X01 := '0';
            VARIABLE TD_K          : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_KNeg         :  X01 := '0';
            VARIABLE TD_KNeg       : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Sviol_KNeg_CNeg    :  X01 := '0';
            VARIABLE SD_KNeg_CNeg  : VitalSkewDataType := VitalSkewDataInit;

            VARIABLE Sviol_K_C          :  X01 := '0';
            VARIABLE SD_K_C        : VitalSkewDataType := VitalSkewDataInit;

            VARIABLE Sviol_K_KNeg       :  X01 := '0';
            VARIABLE SD_K_KNeg     : VitalSkewDataType := VitalSkewDataInit;

            VARIABLE Sviol_C_CNeg       :  X01 := '0';
            VARIABLE SD_C_CNeg     : VitalSkewDataType := VitalSkewDataInit;

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';
            VARIABLE CQ_zd      : std_ulogic := 'U';
            VARIABLE CQNeg_zd   : std_ulogic := 'U';
            VARIABLE CQ_GlitchData    : VitalGlitchDataType;
            VARIABLE CQNeg_GlitchData : VitalGlitchDataType;

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
                             RANGE  -2 TO MaxData;

            VARIABLE MemData0A   : MemStore;
            VARIABLE MemData0B   : MemStore;

            VARIABLE wrop        : boolean := false;
            VARIABLE rdop        : boolean := false;

            VARIABLE waddr       : NATURAL;
            VARIABLE raddr       : NATURAL;

            VARIABLE datatmp     : INTEGER;

            -- No Weak Values Variables
            VARIABLE BWNeg_nwv        : UX01 := 'U';
            VARIABLE BWNeg_reg        : UX01 := 'U';
            VARIABLE RNeg_nwv          : UX01 := 'U';
            VARIABLE WNeg_nwv          : UX01 := 'U';

            VARIABLE dat0_reg          : std_logic_vector(HiDbit downto 0);
            VARIABLE dout_tmpA         : std_logic_vector(HiDbit downto 0):=
                                                            (OTHERS=>'Z');
            VARIABLE dout_tmpB         : std_logic_vector(HiDbit downto 0):=
                                                            (OTHERS=>'Z');
            VARIABLE dout_regA         : std_logic_vector(HiDbit downto 0);
            VARIABLE dout_regB         : std_logic_vector(HiDbit downto 0);

            -- mem file
            FILE mem_file       : text IS mem_file_name;
            VARIABLE ind        : NATURAL := 0;
            VARIABLE buf        : line;

        BEGIN

            BWNeg_nwv     := To_UX01 (s => BWNIn);
            RNeg_nwv       := To_UX01 (s => RInt);
            WNeg_nwv       := To_UX01 (s => WInt);

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => RInt,
                    TestSignalName  => "RNeg",
                    RefSignal       => KIn,
                    RefSignalName   => "K",
                    SetupLow        => tsetup_RNeg_K,
                    HoldLow         => thold_RNeg_K,
                    CheckEnabled    => TRUE,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_RNeg_K,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_RNeg_K );

                VitalSetupHoldCheck (
                    TestSignal      => WInt,
                    TestSignalName  => "WNeg",
                    RefSignal       => KIn,
                    RefSignalName   => "K",
                    SetupLow        => tsetup_RNeg_K,
                    HoldLow         => thold_RNeg_K,
                    CheckEnabled    => TRUE,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_WNeg_K,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_WNeg_K );

                VitalSetupHoldCheck (
                    TestSignal      => BWNIn,
                    TestSignalName  => "BWNeg",
                    RefSignal       => KIn,
                    RefSignalName   => "K",
                    SetupLow        => tsetup_RNeg_K,
                    HoldLow         => thold_RNeg_K,
                    CheckEnabled    => ( WNeg_nwv = '0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_BWNeg_K,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_BWNeg_K );

                VitalSetupHoldCheck (
                    TestSignal      => BWNIn,
                    TestSignalName  => "BWNeg",
                    RefSignal       => KNegIn,
                    RefSignalName   => "KNeg",
                    SetupLow        => tsetup_RNeg_K,
                    HoldLow         => thold_RNeg_K,
                    CheckEnabled    => ( WNeg_nwv = '0'),
                    RefTransition   => '/',