k7r320982m.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: k7r320982m.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2004-2005 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:           | mod date: | changes made:
--    V1.0    V.Ljubisavljevic      04 Aug 16   Initial releas
--    V1.1    V.Ljubisavljevic      05 Feb 22   BWxNeg are now sampled and on
--                                           rising edge of KNeg for burst write
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Technology: CMOS
--  Part:       k7r320982m
--  Description: QDR II SRAM 4M x 9
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
                USE STD.textio.ALL;

LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY k7r320982m IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_DLLNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_ZQ                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A13                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A14                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A15                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A16                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A17                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A18                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A19                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A20                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_RNeg                : VitalDelayType01 := VitalZeroDelay01;
        tipd_WNeg                : VitalDelayType01 := VitalZeroDelay01;
        tipd_BWNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_K                   : VitalDelayType01 := VitalZeroDelay01;
        tipd_KNeg                : VitalDelayType01 := VitalZeroDelay01;
        tipd_C                   : VitalDelayType01 := VitalZeroDelay01;
        tipd_CNeg                : VitalDelayType01 := VitalZeroDelay01;
        tipd_TMS                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_TDI                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_TCK                 : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_C_Q0                 : VitalDelayType01Z := VitalZeroDelay01Z;
        tpd_C_Q1                 : VitalDelayType := UnitDelay;

        tpd_C_CQ                 : VitalDelayType01Z := VitalZeroDelay01Z;
        -- tpw values: pulse widths
        tpw_K_posedge            : VitalDelayType := UnitDelay;
        tpw_K_negedge            : VitalDelayType := UnitDelay;
        -- tperiod min (calculated as 1/max freq)
        tperiod_K                : VitalDelayType := UnitDelay;
        -- tsetup values: setup times
        tsetup_A0_K              : VitalDelayType := UnitDelay;
        tsetup_D0_K              : VitalDelayType := UnitDelay;
        tsetup_RNeg_K            : VitalDelayType := UnitDelay;
        -- thold values: hold times
        thold_A0_K               : VitalDelayType := UnitDelay;
        thold_D0_K               : VitalDelayType := UnitDelay;
        thold_RNeg_K             : VitalDelayType := UnitDelay;

        -- tskew values: skew times
        tskew_K_C                : VitalDelayType := UnitDelay;
        tskew_K_KNeg             : VitalDelayType := UnitDelay;
        tskew_KNeg_K             : VitalDelayType := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        -- memory file to be loaded
        mem_file_name       : STRING    := "k7r323682m.mem";
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        DLLNeg          : IN    std_ulogic := 'U';
        ZQ              : IN    std_ulogic := 'U';
        A0              : IN    std_ulogic := 'U';
        A1              : IN    std_ulogic := 'U';
        A2              : IN    std_ulogic := 'U';
        A3              : IN    std_ulogic := 'U';
        A4              : IN    std_ulogic := 'U';
        A5              : IN    std_ulogic := 'U';
        A6              : IN    std_ulogic := 'U';
        A7              : IN    std_ulogic := 'U';
        A8              : IN    std_ulogic := 'U';
        A9              : IN    std_ulogic := 'U';
        A10             : IN    std_ulogic := 'U';
        A11             : IN    std_ulogic := 'U';
        A12             : IN    std_ulogic := 'U';
        A13             : IN    std_ulogic := 'U';
        A14             : IN    std_ulogic := 'U';
        A15             : IN    std_ulogic := 'U';
        A16             : IN    std_ulogic := 'U';
        A17             : IN    std_ulogic := 'U';
        A18             : IN    std_ulogic := 'U';
        A19             : IN    std_ulogic := 'U';
        A20             : IN    std_ulogic := 'U';
        D0              : IN    std_ulogic := 'U';
        D1              : IN    std_ulogic := 'U';
        D2              : IN    std_ulogic := 'U';
        D3              : IN    std_ulogic := 'U';
        D4              : IN    std_ulogic := 'U';
        D5              : IN    std_ulogic := 'U';
        D6              : IN    std_ulogic := 'U';
        D7              : IN    std_ulogic := 'U';
        D8              : IN    std_ulogic := 'U';
        RNeg            : IN    std_ulogic := 'U';
        WNeg            : IN    std_ulogic := 'U';
        BWNeg           : IN    std_ulogic := 'U';
        K               : IN    std_ulogic := 'U';
        KNeg            : IN    std_ulogic := 'U';
        C               : IN    std_ulogic := 'U';
        CNeg            : IN    std_ulogic := 'U';
        TMS             : IN    std_ulogic := 'U';
        TDI             : IN    std_ulogic := 'U';
        TCK             : IN    std_ulogic := 'U';
        Q0              : OUT   std_ulogic := 'U';
        Q1              : OUT   std_ulogic := 'U';
        Q2              : OUT   std_ulogic := 'U';
        Q3              : OUT   std_ulogic := 'U';
        Q4              : OUT   std_ulogic := 'U';
        Q5              : OUT   std_ulogic := 'U';
        Q6              : OUT   std_ulogic := 'U';
        Q7              : OUT   std_ulogic := 'U';
        Q8              : OUT   std_ulogic := 'U';
        CQ              : OUT   std_ulogic := 'U';
        CQNeg           : OUT   std_ulogic := 'U';
        TDO             : OUT   std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of k7r320982m : ENTITY IS TRUE;
END k7r320982m;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of k7r320982m IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID            : STRING := "k7r320982m";
-- two banks(A and B), each has 2^21 (=2097152)locations
    CONSTANT TotalLOC          : NATURAL := 2097152;
    CONSTANT MaxData           : NATURAL := 511;
    CONSTANT HiAbit            : NATURAL := 20;
    CONSTANT HiDbit            : NATURAL := 8;

    SIGNAL DLLNeg_ipd          : std_ulogic := 'U';
    SIGNAL ZQ_ipd              : std_ulogic := 'U';
    SIGNAL A0_ipd              : std_ulogic := 'U';
    SIGNAL A1_ipd              : std_ulogic := 'U';
    SIGNAL A2_ipd              : std_ulogic := 'U';
    SIGNAL A3_ipd              : std_ulogic := 'U';
    SIGNAL A4_ipd              : std_ulogic := 'U';
    SIGNAL A5_ipd              : std_ulogic := 'U';
    SIGNAL A6_ipd              : std_ulogic := 'U';
    SIGNAL A7_ipd              : std_ulogic := 'U';
    SIGNAL A8_ipd              : std_ulogic := 'U';
    SIGNAL A9_ipd              : std_ulogic := 'U';
    SIGNAL A10_ipd             : std_ulogic := 'U';
    SIGNAL A11_ipd             : std_ulogic := 'U';
    SIGNAL A12_ipd             : std_ulogic := 'U';
    SIGNAL A13_ipd             : std_ulogic := 'U';
    SIGNAL A14_ipd             : std_ulogic := 'U';
    SIGNAL A15_ipd             : std_ulogic := 'U';
    SIGNAL A16_ipd             : std_ulogic := 'U';
    SIGNAL A17_ipd             : std_ulogic := 'U';
    SIGNAL A18_ipd             : std_ulogic := 'U';
    SIGNAL A19_ipd             : std_ulogic := 'U';
    SIGNAL A20_ipd             : std_ulogic := 'U';
    SIGNAL D0_ipd              : std_ulogic := 'U';
    SIGNAL D1_ipd              : std_ulogic := 'U';
    SIGNAL D2_ipd              : std_ulogic := 'U';
    SIGNAL D3_ipd              : std_ulogic := 'U';
    SIGNAL D4_ipd              : std_ulogic := 'U';
    SIGNAL D5_ipd              : std_ulogic := 'U';
    SIGNAL D6_ipd              : std_ulogic := 'U';
    SIGNAL D7_ipd              : std_ulogic := 'U';
    SIGNAL D8_ipd              : std_ulogic := 'U';
    SIGNAL RNeg_ipd            : std_ulogic := 'U';
    SIGNAL WNeg_ipd            : std_ulogic := 'U';
    SIGNAL BWNeg_ipd           : std_ulogic := 'U';
    SIGNAL K_ipd               : std_ulogic := 'U';
    SIGNAL KNeg_ipd            : std_ulogic := 'U';
    SIGNAL C_ipd               : std_ulogic := 'U';
    SIGNAL CNeg_ipd            : std_ulogic := 'U';
    SIGNAL TMS_ipd             : std_ulogic := 'U';
    SIGNAL TDI_ipd             : std_ulogic := 'U';
    SIGNAL TCK_ipd             : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
        w_1 : VitalWireDelay (DLLNeg_ipd, DLLNeg, tipd_DLLNeg);
        w_2 : VitalWireDelay (ZQ_ipd, ZQ, tipd_ZQ);
        w_3 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_4 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_5 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_6 : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_7 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_8 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_9 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_10 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_11 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_12 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_13 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_14 : VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_15 : VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_16 : VitalWireDelay (A13_ipd, A13, tipd_A13);
        w_17 : VitalWireDelay (A14_ipd, A14, tipd_A14);
        w_18 : VitalWireDelay (A15_ipd, A15, tipd_A15);
        w_19 : VitalWireDelay (A16_ipd, A16, tipd_A16);
        w_20 : VitalWireDelay (A17_ipd, A17, tipd_A17);
        w_21 : VitalWireDelay (A18_ipd, A18, tipd_A18);
        w_22 : VitalWireDelay (A19_ipd, A19, tipd_A19);
        w_23 : VitalWireDelay (A20_ipd, A20, tipd_A20);
        w_25 : VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_26 : VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_27 : VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_28 : VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_29 : VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_30 : VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_31 : VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_32 : VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_33 : VitalWireDelay (D8_ipd, D8, tipd_D8);
        w_61 : VitalWireDelay (RNeg_ipd, RNeg, tipd_RNeg);
        w_62 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
        w_63 : VitalWireDelay (BWNeg_ipd, BWNeg, tipd_BWNeg);
        w_67 : VitalWireDelay (K_ipd, K, tipd_K);
        w_68 : VitalWireDelay (KNeg_ipd, KNeg, tipd_KNeg);
        w_69 : VitalWireDelay (C_ipd, C, tipd_C);
        w_70 : VitalWireDelay (CNeg_ipd, CNeg, tipd_CNeg);
        w_71 : VitalWireDelay (TMS_ipd, TMS, tipd_TMS);
        w_72 : VitalWireDelay (TDI_ipd, TDI, tipd_TDI);
        w_73 : VitalWireDelay (TCK_ipd, TCK, tipd_TCK);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK
        PORT (
            DLLNegIn        : IN    std_logic  := 'U';
            BWNIn          : IN    std_ulogic := 'U';
            Dat0In          : IN    std_logic_vector(HiDbit downto 0);
            DataOut         : OUT   std_logic_vector(HiDbit downto 0)
                                                     := (others => 'Z');
            CIn             : IN    std_ulogic := 'U';
            CNegIn          : IN    std_ulogic := 'U';
            KIn             : IN    std_ulogic := 'U';
            KNegIn          : IN    std_ulogic := 'U';
            AddressIn       : IN    std_logic_vector(HiAbit downto 0);
            RInt            : IN    std_ulogic := 'U';
            WInt            : IN    std_ulogic := 'U';
            CQOut           : OUT   std_ulogic := 'U';
            CQNegOut        : OUT   std_ulogic := 'U'
        );
        PORT MAP (
            Dat0In(0) => D0_ipd,
            Dat0In(1) => D1_ipd,
            Dat0In(2) => D2_ipd,
            Dat0In(3) => D3_ipd,
            Dat0In(4) => D4_ipd,
            Dat0In(5) => D5_ipd,
            Dat0In(6) => D6_ipd,
            Dat0In(7) => D7_ipd,
            Dat0In(8) => D8_ipd,
            DataOut(0) =>  Q0,
            DataOut(1) =>  Q1,
            DataOut(2) =>  Q2,
            DataOut(3) =>  Q3,
            DataOut(4) =>  Q4,
            DataOut(5) =>  Q5,
            DataOut(6) =>  Q6,
            DataOut(7) =>  Q7,
            DataOut(8) =>  Q8,
            AddressIn(0) => A0_ipd,
            AddressIn(1) => A1_ipd,
            AddressIn(2) => A2_ipd,
            AddressIn(3) => A3_ipd,
            AddressIn(4) => A4_ipd,
            AddressIn(5) => A5_ipd,
            AddressIn(6) => A6_ipd,
            AddressIn(7) => A7_ipd,
            AddressIn(8) => A8_ipd,
            AddressIn(9) => A9_ipd,
            AddressIn(10) => A10_ipd,
            AddressIn(11) => A11_ipd,
            AddressIn(12) => A12_ipd,
            AddressIn(13) => A13_ipd,
            AddressIn(14) => A14_ipd,
            AddressIn(15) => A15_ipd,
            AddressIn(16) => A16_ipd,
            AddressIn(17) => A17_ipd,
            AddressIn(18) => A18_ipd,
            AddressIn(19) => A19_ipd,
            AddressIn(20) => A20_ipd,
            BWNIn => BWNeg_ipd,
            CIn => C_ipd,
            CNegIn => CNeg_ipd,
            KIn => K_ipd,
            KNegIn => KNeg_ipd,
            RInt => RNeg_ipd,
            WInt => WNeg_ipd,
            CQOut => CQ,
            CQNegOut => CQNeg,
            DLLNegIn => DLLNeg_ipd
        );

        SIGNAL Q_zd     : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL KTRIG    : std_ulogic;