cy7c131.vhd

vhdl cod for ram.For sp3e

                    TestSignal      => IOLIn,
                    TestSignalName  => "IOL",
                    RefSignal       => RWLIn,
                    RefSignalName   => "RWL",
                    SetupHigh       => tsetup_IOL0_RWL,
                    SetupLow        => tsetup_IOL0_RWL,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_IOLIn_RWLIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_IOLIn_RWLIn );

                VitalSetupHoldCheck (
                    TestSignal      => IORIn,
                    TestSignalName  => "IOR",
                    RefSignal       => RWRIn,
                    RefSignalName   => "RWR",
                    SetupHigh       => tsetup_IOL0_RWL,
                    SetupLow        => tsetup_IOL0_RWL,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_IORIn_RWRIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_IORIn_RWRIn );

                VitalPeriodPulseCheck (
                    TestSignal      =>  RWLIn,
                    TestSignalName  =>  "RWL",
                    PulseWidthLow   =>  tpw_RWL_negedge,
                    PeriodData      =>  PD_RWLIn,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_RWLIn,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE );

                VitalPeriodPulseCheck (
                    TestSignal      =>  RWRIn,
                    TestSignalName  =>  "RWR",
                    PulseWidthLow   =>  tpw_RWL_negedge,
                    PeriodData      =>  PD_RWRIn,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_RWRIn,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE );

               Violation := Tviol_ALIn_CELNegIn OR Tviol_ALIn_RWLInL OR
                            Tviol_ALIn_RWLInH OR Tviol_ARIn_CERNegIn OR
                            Tviol_ARIn_RWRInL OR Tviol_ARIn_RWRInH OR
                            Tviol_CELNegIn_RWLIn OR Tviol_CERNegIn_RWRIn OR
                            Tviol_IOLIn_RWLIn OR Pviol_RWLIn OR 
                            Tviol_IORIn_RWRIn OR Pviol_RWRIn;

                ASSERT Violation = '0'
                    REPORT InstancePath & partID & ": simulation may be" &
                           " inaccurate due to timing violations"
                    SEVERITY SeverityMode;

            END IF; -- Timing Check Section

            --------------------------------------------------------------------
            -- Functional Section
            --------------------------------------------------------------------
            DataLDrive := (OTHERS => 'Z');
            DataRDrive := (OTHERS => 'Z');

            IF (CELNeg_nwv = '0' AND CERNeg_nwv = '0') THEN
                IF To_Nat(ALIn) = To_Nat(ARIn) THEN
                    IF (ALIn'EVENT OR CELNegIn'EVENT) THEN
                        BUSYL_zd := '0';
                    ELSIF (ARIn'EVENT OR CERNegIn'EVENT) THEN
                        BUSYR_zd := '0';
                    END IF;
                ELSE
                    BUSYL_zd := '1';
                    BUSYR_zd := '1';
                END IF;
            ELSE
                BUSYL_zd := '1';
                BUSYR_zd := '1';
            END IF;

            IF rising_edge(WRTL_int) THEN
                IF Violation = '0' THEN
                    DataTempL := To_Nat(IOLIn);
                ELSE
                    DataTempL := -1;
                END IF;
                MemData(Location) := DataTempL;
            ELSIF (CELNeg_nwv = '0') THEN
                IF (OELNeg_nwv = '0' OR RWL_nwv = '0') THEN

                    Location := To_Nat(ALIn);

                    IF (OELNeg_nwv = '0' AND RWL_nwv = '1') THEN
                        DataTempL := MemData(Location);
                        IF DataTempL >= 0 THEN
                            DataLDrive := To_slv(DataTempL, DataWidth);
                        ELSIF DataTempL = -2 THEN
                            DataLDrive := (OTHERS => 'U');
                        ELSE
                            DataLDrive := (OTHERS => 'X');
                        END IF;
                    END IF;
                END IF;

                IF RWL_nwv = '0' AND Location = 16#3FF# THEN
                    IF BUSYL_zd = '1' THEN
                        INTR_zd := '0';
                    END IF;
                END IF;
                IF (OELNeg_nwv = '0' AND Location = 16#3FF#) THEN
                    IF BUSYL_zd = '1' THEN
                        INTL_zd := '1';
                    END IF;
                END IF;

            END IF;

            IF rising_edge(WRTR_int) THEN
                IF Violation = '0' THEN
                    DataTempR := To_Nat(IORIn);
                ELSE
                    DataTempR := -1;
                END IF;
                MemData(Location) := DataTempR;
            ELSIF (CERNeg_nwv = '0') THEN
                IF (OERNeg_nwv = '0' OR RWR_nwv = '0') THEN

                    Location := To_Nat(ARIn);

                    IF (OERNeg_nwv = '0' AND RWR_nwv = '1') THEN
                        DataTempR := MemData(Location);
                        IF DataTempR >= 0 THEN
                            DataRDrive := To_slv(DataTempR, DataWidth);
                        ELSIF DataTempR = -2 THEN
                            DataRDrive := (OTHERS => 'U');
                        ELSE
                            DataRDrive := (OTHERS => 'X');
                        END IF;
                    END IF;

                IF RWR_nwv = '0' AND Location = 16#3FF# THEN
                    IF BUSYR_zd = '1' THEN
                        INTL_zd := '0';
                    END IF;
                END IF;
                IF (OERNeg_nwv = '0' AND Location = 16#3FF#) THEN
                    IF BUSYL_zd = '1' THEN
                        INTR_zd := '1';
                    END IF;
                END IF;

                END IF;
            END IF;

            --------------------------------------------------------------------
            -- Output Section
            --------------------------------------------------------------------
            IOL_zd <= DataLDrive;
            IOR_zd <= DataRDrive;

        VitalPathDelay01 (
            OutSignal       => INTLNeg,
            OutSignalName   => "INTL",
            OutTemp         => INTL_zd,
            GlitchData      => INTL_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => ALIn'LAST_EVENT,
                     PathDelay         => tpd_AL0_INTLNeg,
                     PathCondition     => TRUE),
                1 => (InputChangeTime   => RWRIn'LAST_EVENT,
                     PathDelay         => tpd_RWL_INTRNeg,
                     PathCondition     => TRUE),
                2 => (InputChangeTime   => CELNeg'LAST_EVENT,
                     PathDelay         => tpd_RWL_INTRNeg,
                     PathCondition     => TRUE),
                3 => (InputChangeTime   => OELNeg'LAST_EVENT,
                     PathDelay         => tpd_RWL_INTRNeg,
                     PathCondition     => TRUE))
        );

        VitalPathDelay01 (
            OutSignal       => INTRNeg,
            OutSignalName   => "INTR",
            OutTemp         => INTR_zd,
            GlitchData      => INTR_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => ARIn'LAST_EVENT,
                     PathDelay         => tpd_AL0_INTLNeg,
                     PathCondition     => TRUE),
                1 => (InputChangeTime   => RWLIn'LAST_EVENT,
                     PathDelay         => tpd_RWL_INTRNeg,
                     PathCondition     => TRUE),
                2 => (InputChangeTime   => CERNeg'LAST_EVENT,
                     PathDelay         => tpd_RWL_INTRNeg,
                     PathCondition     => TRUE),
                3 => (InputChangeTime   => OERNeg'LAST_EVENT,
                     PathDelay         => tpd_RWL_INTRNeg,
                     PathCondition     => TRUE))
        );

        VitalPathDelay01 (
            OutSignal       => BUSYLNeg,
            OutSignalName   => "BUSYL",
            OutTemp         => BUSYL_zd,
            GlitchData      => BUSYL_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => ARIn'LAST_EVENT,
                     PathDelay         => tpd_AL0_BUSYLNeg,
                     PathCondition     => TRUE),
                1 => (InputChangeTime   => ALIn'LAST_EVENT,
                     PathDelay         => tpd_AL0_BUSYLNeg,
                     PathCondition     => TRUE),
                2 => (InputChangeTime   => CERNeg'LAST_EVENT,
                     PathDelay         => tpd_CELNeg_BUSYLNeg,
                     PathCondition     => TRUE),
                3 => (InputChangeTime   => CELNeg'LAST_EVENT,
                     PathDelay         => tpd_CELNeg_BUSYLNeg,
                     PathCondition     => TRUE))
        );

        VitalPathDelay01 (
            OutSignal       => BUSYRNeg,
            OutSignalName   => "BUSYR",
            OutTemp         => BUSYR_zd,
            GlitchData      => BUSYR_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => ARIn'LAST_EVENT,
                     PathDelay         => tpd_AL0_BUSYLNeg,
                     PathCondition     => TRUE),
                1 => (InputChangeTime   => ALIn'LAST_EVENT,
                     PathDelay         => tpd_AL0_BUSYLNeg,
                     PathCondition     => TRUE),
                2 => (InputChangeTime   => CELNeg'LAST_EVENT,
                     PathDelay         => tpd_CELNeg_BUSYLNeg,
                     PathCondition     => TRUE),
                3 => (InputChangeTime   => CERNeg'LAST_EVENT,
                     PathDelay         => tpd_CELNeg_BUSYLNeg,
                     PathCondition     => TRUE))
        );

        END PROCESS;

        ------------------------------------------------------------------------
        -- Path Delay Processes generated as a function of data width
        ------------------------------------------------------------------------
        DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE
            DataOut_Delay : PROCESS (IOR_zd(i), IOL_zd(i))
              VARIABLE IOR_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
              VARIABLE IOL_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
            BEGIN
                VitalPathDelay01Z (
                    OutSignal       => IOLOut(i),
                    OutSignalName   => "IOL",
                    OutTemp         => IOL_zd(i),
                    Mode            => OnEvent,
                    GlitchData      => IOL_GlitchData(i),
                    Paths           => (
                        0 => (InputChangeTime => OELNeg'LAST_EVENT,
                              PathDelay       => tpd_OELNeg_IOL0,
                              PathCondition   => TRUE),
                        1 => (InputChangeTime => CELNeg'LAST_EVENT,
                              PathDelay       => tpd_CELNeg_IOL0,
                              PathCondition   => TRUE),
                        2 => (InputChangeTime => ALIn'LAST_EVENT,
                              PathDelay       => 
                                  VitalExtendToFillDelay(tpd_AL0_IOL0),
                              PathCondition   => TRUE)
                   )
               );

                VitalPathDelay01Z (
                    OutSignal       => IOROut(i),
                    OutSignalName   => "IOR",
                    OutTemp         => IOR_zd(i),
                    Mode            => OnEvent,
                    GlitchData      => IOR_GlitchData(i),
                    Paths           => (
                        0 => (InputChangeTime => OERNeg'LAST_EVENT,
                              PathDelay       => tpd_OELNeg_IOL0,
                              PathCondition   => TRUE),
                        1 => (InputChangeTime => CERNeg'LAST_EVENT,
                              PathDelay       => tpd_CELNeg_IOL0,
                              PathCondition   => TRUE),
                        2 => (InputChangeTime => ARIn'LAST_EVENT,
                              PathDelay       => 
                                  VitalExtendToFillDelay(tpd_AL0_IOL0),
                              PathCondition   => TRUE)
                   )
               );

            END PROCESS;
        END GENERATE;


    END BLOCK;
END vhdl_behavioral;