cy7c131.vhd

vhdl cod for ram.For sp3e

            ARIn(5) =>  AR5_ipd,
            ARIn(6) =>  AR6_ipd,
            ARIn(7) =>  AR7_ipd,
            ARIn(8) =>  AR8_ipd,
            ARIn(9) =>  AR9_ipd,
            IOLIn(0) => IOL0_ipd,
            IOLIn(1) => IOL1_ipd,
            IOLIn(2) => IOL2_ipd,
            IOLIn(3) => IOL3_ipd,
            IOLIn(4) => IOL4_ipd,
            IOLIn(5) => IOL5_ipd,
            IOLIn(6) => IOL6_ipd,
            IOLIn(7) => IOL7_ipd,
            IORIn(0) => IOR0_ipd,
            IORIn(1) => IOR1_ipd,
            IORIn(2) => IOR2_ipd,
            IORIn(3) => IOR3_ipd,
            IORIn(4) => IOR4_ipd,
            IORIn(5) => IOR5_ipd,
            IORIn(6) => IOR6_ipd,
            IORIn(7) => IOR7_ipd,
            IOLOut(0) => IOL0,
            IOLOut(1) => IOL1,
            IOLOut(2) => IOL2,
            IOLOut(3) => IOL3,
            IOLOut(4) => IOL4,
            IOLOut(5) => IOL5,
            IOLOut(6) => IOL6,
            IOLOut(7) => IOL7,
            IOROut(0) => IOR0,
            IOROut(1) => IOR1,
            IOROut(2) => IOR2,
            IOROut(3) => IOR3,
            IOROut(4) => IOR4,
            IOROut(5) => IOR5,
            IOROut(6) => IOR6,
            IOROut(7) => IOR7,
            RWLIn     => RWL_ipd,
            RWRIn     => RWR_ipd,
            OELNegIn  => OELNeg_ipd,
            OERNegIn  => OERNeg_ipd,
            CELNegIn  => CELNeg_ipd,
            CERNegIn  => CERNeg_ipd,
            BUSYLNeg  => BUSYLNeg,
            BUSYRNeg  => BUSYRNeg,
            INTLNeg   => INTLNeg,
            INTRNeg   => INTRNeg
        );

        SIGNAL IOL_zd    : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL IOR_zd    : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL WRTL_int  : std_ulogic := '1';
        SIGNAL WRTR_int  : std_ulogic := '1';

    BEGIN

        WRTL_int <= RWLIn OR CELNegIn;
        WRTR_int <= RWRIn OR CERNegIn;

        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Memory : PROCESS (OELNegIn, OERNegIn, RWLIn, RWRIn, CELNegIn, CERNegIn,
                          ALIn, ARIn, IOLIn, IORIn, WRTL_int, WRTR_int)

            -- Timing Check Variables
            VARIABLE Tviol_ALIn_CELNegIn  : X01 := '0';
            VARIABLE TD_ALIn_CELNegIn     : VitalTimingDataType;

            VARIABLE Tviol_ALIn_CELNegInH : X01 := '0';
            VARIABLE TD_ALIn_CELNegInH    : VitalTimingDataType;

            VARIABLE Tviol_ALIn_RWLInL    : X01 := '0';
            VARIABLE TD_ALIn_RWLInL       : VitalTimingDataType;

            VARIABLE Tviol_ALIn_RWLInH    : X01 := '0';
            VARIABLE TD_ALIn_RWLInH       : VitalTimingDataType;

            VARIABLE Tviol_ARIn_CERNegIn  : X01 := '0';
            VARIABLE TD_ARIn_CERNegIn     : VitalTimingDataType;

            VARIABLE Tviol_ARIn_CERNegInH : X01 := '0';
            VARIABLE TD_ARIn_CERNegInH    : VitalTimingDataType;

            VARIABLE Tviol_ARIn_RWRInL    : X01 := '0';
            VARIABLE TD_ARIn_RWRInL       : VitalTimingDataType;

            VARIABLE Tviol_ARIn_RWRInH    : X01 := '0';
            VARIABLE TD_ARIn_RWRInH       : VitalTimingDataType;

            VARIABLE Tviol_CELNegIn_RWLIn : X01 := '0';
            VARIABLE TD_CELNegIn_RWLIn    : VitalTimingDataType;

            VARIABLE Tviol_CERNegIn_RWRIn : X01 := '0';
            VARIABLE TD_CERNegIn_RWRIn    : VitalTimingDataType;

            VARIABLE Tviol_IOLIn_RWLIn    : X01 := '0';
            VARIABLE TD_IOLIn_RWLIn       : VitalTimingDataType;

            VARIABLE Tviol_IORIn_RWRIn    : X01 := '0';
            VARIABLE TD_IORIn_RWRIn       : VitalTimingDataType;

            VARIABLE Pviol_RWLIn          : X01 := '0';
            VARIABLE PD_RWLIn      : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_RWRIn          : X01 := '0';
            VARIABLE PD_RWRIn      : VitalPeriodDataType := VitalPeriodDataInit;

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
                             RANGE  -2 TO MaxData;

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';

            VARIABLE BUSYL_zd   : std_logic;
            VARIABLE BUSYR_zd   : std_logic;
            VARIABLE INTL_zd    : std_logic;
            VARIABLE INTR_zd    : std_logic;
            VARIABLE DataLDrive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'X');
            VARIABLE DataRDrive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'X');
            VARIABLE DataTempL  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE DataTempR  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE Location   : NATURAL RANGE 0 TO TotalLOC := 0;
            VARIABLE MemData    : MemStore;

            -- Output Glitch Detection Variables
            VARIABLE INTL_GlitchData     : VitalGlitchDataType;
            VARIABLE INTR_GlitchData     : VitalGlitchDataType;
            VARIABLE BUSYL_GlitchData    : VitalGlitchDataType;
            VARIABLE BUSYR_GlitchData    : VitalGlitchDataType;

            -- No Weak Values Variables
            VARIABLE CELNeg_nwv   : UX01 := 'X';
            VARIABLE CERNeg_nwv   : UX01 := 'X';
            VARIABLE OELNeg_nwv   : UX01 := 'X';
            VARIABLE OERNeg_nwv   : UX01 := 'X';
            VARIABLE RWL_nwv      : UX01 := 'X';
            VARIABLE RWR_nwv      : UX01 := 'X';

        BEGIN
            CELNeg_nwv  := To_UX01 (s => CELNegIn);
            CERNeg_nwv  := To_UX01 (s => CERNegIn);
            OELNeg_nwv  := To_UX01 (s => OELNegIn);
            OERNeg_nwv  := To_UX01 (s => OERNegIn);
            RWL_nwv     := To_UX01 (s => RWLIn);
            RWR_nwv     := To_UX01 (s => RWRIn);

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => ALIn,
                    TestSignalName  => "AL",
                    RefSignal       => CELNegIn,
                    RefSignalName   => "CELNeg",
                    SetupHigh       => tsetup_AL0_CELNeg,
                    SetupLow        => tsetup_AL0_CELNeg,
                    CheckEnabled    => (RWLIn ='0'),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ALIn_CELNegIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ALIn_CELNegIn );

                VitalSetupHoldCheck (
                    TestSignal      => ARIn,
                    TestSignalName  => "AR",
                    RefSignal       => CERNegIn,
                    RefSignalName   => "CERNeg",
                    SetupHigh       => tsetup_AL0_CELNeg,
                    SetupLow        => tsetup_AL0_CELNeg,
                    CheckEnabled    => (RWRIn ='0'),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ARIn_CERNegIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ARIn_CERNegIn );

                VitalSetupHoldCheck (
                    TestSignal      => ALIn,
                    TestSignalName  => "AL",
                    RefSignal       => RWLIn,
                    RefSignalName   => "RWL",
                    SetupHigh       => tsetup_AL0_RWL,
                    SetupLow        => tsetup_AL0_RWL,
                    CheckEnabled    => (CELNegIn ='0'),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ALIn_RWLInL,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ALIn_RWLInL );

                VitalSetupHoldCheck (
                    TestSignal      => ARIn,
                    TestSignalName  => "AR",
                    RefSignal       => RWRIn,
                    RefSignalName   => "RWR",
                    SetupHigh       => tsetup_AL0_RWL,
                    SetupLow        => tsetup_AL0_RWL,
                    CheckEnabled    => (CERNegIn ='0'),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ARIn_RWRInL,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ARIn_RWRInL );

                VitalSetupHoldCheck (
                    TestSignal      => ALIn,
                    TestSignalName  => "AL",
                    RefSignal       => CELNegIn,
                    RefSignalName   => "CELNeg",
                    SetupHigh       => tsetup_AL1_RWL,
                    SetupLow        => tsetup_AL1_RWL,
                    HoldHigh        => thold_AL0_CELNeg,
                    HoldLow         => thold_AL0_CELNeg,
                    CheckEnabled    => (RWLIn ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ALIn_CELNegIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ALIn_CELNegIn );

                VitalSetupHoldCheck (
                    TestSignal      => ARIn,
                    TestSignalName  => "AR",
                    RefSignal       => CERNegIn,
                    RefSignalName   => "CERNeg",
                    SetupHigh       => tsetup_AL1_RWL,
                    SetupLow        => tsetup_AL1_RWL,
                    HoldHigh        => thold_AL0_CELNeg,
                    HoldLow         => thold_AL0_CELNeg,
                    CheckEnabled    => (RWRIn ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ARIn_CERNegInH,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ARIn_CERNegInH );

                VitalSetupHoldCheck (
                    TestSignal      => ALIn,
                    TestSignalName  => "AL",
                    RefSignal       => RWLIn,
                    RefSignalName   => "RWL",
                    SetupHigh       => tsetup_AL1_RWL,
                    SetupLow        => tsetup_AL1_RWL,
                    HoldHigh        => thold_AL0_CELNeg,
                    HoldLow         => thold_AL0_CELNeg,
                    CheckEnabled    => (CELNegIn ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ALIn_RWLInH,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ALIn_RWLInH );

                VitalSetupHoldCheck (
                    TestSignal      => ARIn,
                    TestSignalName  => "AR",
                    RefSignal       => RWRIn,
                    RefSignalName   => "RWR",
                    SetupHigh       => tsetup_AL1_RWL,
                    SetupLow        => tsetup_AL1_RWL,
                    HoldHigh        => thold_AL0_CELNeg,
                    HoldLow         => thold_AL0_CELNeg,
                    CheckEnabled    => (CERNegIn ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ARIn_RWRInH,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ARIn_RWRInH );

                VitalSetupHoldCheck (
                    TestSignal      => CELNegIn,
                    TestSignalName  => "CELNeg",
                    RefSignal       => RWLIn,
                    RefSignalName   => "RWL",
                    SetupLow        => tsetup_CELNeg_RWL,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CELNegIn_RWLIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CELNegIn_RWLIn );

                VitalSetupHoldCheck (
                    TestSignal      => CERNegIn,
                    TestSignalName  => "CERNeg",
                    RefSignal       => RWRIn,
                    RefSignalName   => "RWR",
                    SetupLow        => tsetup_CELNeg_RWL,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CERNegIn_RWRIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CERNegIn_RWRIn );

                VitalSetupHoldCheck (