cy7c131.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: cy7c131.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2000-2008 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    00 APR 05   Initial release
--    V1.1    R. Munden    08 MAY 23   Correct tsetup_IOL0_RWL generic name
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    RAM
--  Technology: SRAM
--  Part:       CY7C131
-- 
--  Description: SRAM DUAL-PORT 1K X 8
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY cy7c131 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_RWR                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_RWL                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_OERNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_OELNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR7                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR6                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR5                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR4                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR3                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR2                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR1                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR0                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL7                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL6                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL5                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL4                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL3                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL2                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL1                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL0                : VitalDelayType01 := VitalZeroDelay01;
        tipd_CERNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CELNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_BUSYRNeg            : VitalDelayType01 := VitalZeroDelay01;
        tipd_BUSYLNeg            : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL0                 : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_RWL_INTRNeg          : VitalDelayType01 := UnitDelay01;
        tpd_OELNeg_IOL0          : VitalDelayType01Z := UnitDelay01Z;
        tpd_CELNeg_IOL0          : VitalDelayType01Z := UnitDelay01Z;
        tpd_AL0_INTLNeg          : VitalDelayType01 := UnitDelay01;
        tpd_AL0_IOL0             : VitalDelayType01 := UnitDelay01;
        tpd_AL0_BUSYLNeg         : VitalDelayType01 := UnitDelay01;
        tpd_CELNeg_BUSYLNeg      : VitalDelayType01 := UnitDelay01;
        -- tpw values: pulse widths
        tpw_RWL_negedge          : VitalDelayType    := UnitDelay;
        -- tsetup values: setup times
        -- tAS
        tsetup_AL0_CELNeg        : VitalDelayType    := UnitDelay;
        tsetup_AL0_RWL           : VitalDelayType    := UnitDelay;
        -- tAW
        tsetup_AL1_RWL           : VitalDelayType    := UnitDelay;
        -- tEW
        tsetup_CELNeg_RWL        : VitalDelayType    := UnitDelay;
        -- tDW
        tsetup_IOL0_RWL          : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        -- tWR
        thold_AL0_CELNeg         : VitalDelayType    := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        RWR             : IN    std_logic := 'U';
        RWL             : IN    std_logic := 'U';
        OERNeg          : IN    std_logic := 'U';
        OELNeg          : IN    std_logic := 'U';
        INTRNeg         : OUT   std_logic := '1';
        INTLNeg         : OUT   std_logic := '1';
        IOR7            : INOUT std_logic := 'U';
        IOR6            : INOUT std_logic := 'U';
        IOR5            : INOUT std_logic := 'U';
        IOR4            : INOUT std_logic := 'U';
        IOR3            : INOUT std_logic := 'U';
        IOR2            : INOUT std_logic := 'U';
        IOR1            : INOUT std_logic := 'U';
        IOR0            : INOUT std_logic := 'U';
        IOL7            : INOUT std_logic := 'U';
        IOL6            : INOUT std_logic := 'U';
        IOL5            : INOUT std_logic := 'U';
        IOL4            : INOUT std_logic := 'U';
        IOL3            : INOUT std_logic := 'U';
        IOL2            : INOUT std_logic := 'U';
        IOL1            : INOUT std_logic := 'U';
        IOL0            : INOUT std_logic := 'U';
        CERNeg          : IN    std_logic := 'U';
        CELNeg          : IN    std_logic := 'U';
        BUSYRNeg        : OUT   std_logic := '1';
        BUSYLNeg        : OUT   std_logic := '1';
        AR9             : IN    std_logic := 'U';
        AL9             : IN    std_logic := 'U';
        AR8             : IN    std_logic := 'U';
        AL8             : IN    std_logic := 'U';
        AR7             : IN    std_logic := 'U';
        AL7             : IN    std_logic := 'U';
        AR6             : IN    std_logic := 'U';
        AL6             : IN    std_logic := 'U';
        AR5             : IN    std_logic := 'U';
        AL5             : IN    std_logic := 'U';
        AR4             : IN    std_logic := 'U';
        AL4             : IN    std_logic := 'U';
        AR3             : IN    std_logic := 'U';
        AL3             : IN    std_logic := 'U';
        AR2             : IN    std_logic := 'U';
        AL2             : IN    std_logic := 'U';
        AR1             : IN    std_logic := 'U';
        AL1             : IN    std_logic := 'U';
        AR0             : IN    std_logic := 'U';
        AL0             : IN    std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of cy7c131 : ENTITY IS TRUE;
END cy7c131;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of cy7c131 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "CY7C131";
    CONSTANT MaxData        : NATURAL := 255;
    CONSTANT TotalLOC       : NATURAL := 1023;
    CONSTANT HiAbit         : NATURAL := 9;
    CONSTANT HiDbit         : NATURAL := 7;
    CONSTANT DataWidth      : NATURAL := 8;

    SIGNAL RWR_ipd             : std_ulogic := 'U';
    SIGNAL RWL_ipd             : std_ulogic := 'U';
    SIGNAL OERNeg_ipd          : std_ulogic := 'U';
    SIGNAL OELNeg_ipd          : std_ulogic := 'U';
    SIGNAL IOR7_ipd            : std_ulogic := 'U';
    SIGNAL IOR6_ipd            : std_ulogic := 'U';
    SIGNAL IOR5_ipd            : std_ulogic := 'U';
    SIGNAL IOR4_ipd            : std_ulogic := 'U';
    SIGNAL IOR3_ipd            : std_ulogic := 'U';
    SIGNAL IOR2_ipd            : std_ulogic := 'U';
    SIGNAL IOR1_ipd            : std_ulogic := 'U';
    SIGNAL IOR0_ipd            : std_ulogic := 'U';
    SIGNAL IOL7_ipd            : std_ulogic := 'U';
    SIGNAL IOL6_ipd            : std_ulogic := 'U';
    SIGNAL IOL5_ipd            : std_ulogic := 'U';
    SIGNAL IOL4_ipd            : std_ulogic := 'U';
    SIGNAL IOL3_ipd            : std_ulogic := 'U';
    SIGNAL IOL2_ipd            : std_ulogic := 'U';
    SIGNAL IOL1_ipd            : std_ulogic := 'U';
    SIGNAL IOL0_ipd            : std_ulogic := 'U';
    SIGNAL CERNeg_ipd          : std_ulogic := 'U';
    SIGNAL CELNeg_ipd          : std_ulogic := 'U';
    SIGNAL AR9_ipd             : std_ulogic := 'U';
    SIGNAL AL9_ipd             : std_ulogic := 'U';
    SIGNAL AR8_ipd             : std_ulogic := 'U';
    SIGNAL AL8_ipd             : std_ulogic := 'U';
    SIGNAL AR7_ipd             : std_ulogic := 'U';
    SIGNAL AL7_ipd             : std_ulogic := 'U';
    SIGNAL AR6_ipd             : std_ulogic := 'U';
    SIGNAL AL6_ipd             : std_ulogic := 'U';
    SIGNAL AR5_ipd             : std_ulogic := 'U';
    SIGNAL AL5_ipd             : std_ulogic := 'U';
    SIGNAL AR4_ipd             : std_ulogic := 'U';
    SIGNAL AL4_ipd             : std_ulogic := 'U';
    SIGNAL AR3_ipd             : std_ulogic := 'U';
    SIGNAL AL3_ipd             : std_ulogic := 'U';
    SIGNAL AR2_ipd             : std_ulogic := 'U';
    SIGNAL AL2_ipd             : std_ulogic := 'U';
    SIGNAL AR1_ipd             : std_ulogic := 'U';
    SIGNAL AL1_ipd             : std_ulogic := 'U';
    SIGNAL AR0_ipd             : std_ulogic := 'U';
    SIGNAL AL0_ipd             : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (RWR_ipd, RWR, tipd_RWR);
        w_2 : VitalWireDelay (RWL_ipd, RWL, tipd_RWL);
        w_3 : VitalWireDelay (OERNeg_ipd, OERNeg, tipd_OERNeg);
        w_4 : VitalWireDelay (OELNeg_ipd, OELNeg, tipd_OELNeg);
        w_9 : VitalWireDelay (CERNeg_ipd, CERNeg, tipd_CERNeg);
        w_10 : VitalWireDelay (CELNeg_ipd, CELNeg, tipd_CELNeg);
        w_13 : VitalWireDelay (AR9_ipd, AR9, tipd_AR9);
        w_14 : VitalWireDelay (AL9_ipd, AL9, tipd_AL9);
        w_15 : VitalWireDelay (AR8_ipd, AR8, tipd_AR8);
        w_16 : VitalWireDelay (AL8_ipd, AL8, tipd_AL8);
        w_17 : VitalWireDelay (AR7_ipd, AR7, tipd_AR7);
        w_18 : VitalWireDelay (AL7_ipd, AL7, tipd_AL7);
        w_19 : VitalWireDelay (AR6_ipd, AR6, tipd_AR6);
        w_20 : VitalWireDelay (AL6_ipd, AL6, tipd_AL6);
        w_21 : VitalWireDelay (AR5_ipd, AR5, tipd_AR5);
        w_22 : VitalWireDelay (AL5_ipd, AL5, tipd_AL5);
        w_23 : VitalWireDelay (AR4_ipd, AR4, tipd_AR4);
        w_24 : VitalWireDelay (AL4_ipd, AL4, tipd_AL4);
        w_25 : VitalWireDelay (AR3_ipd, AR3, tipd_AR3);
        w_26 : VitalWireDelay (AL3_ipd, AL3, tipd_AL3);
        w_27 : VitalWireDelay (AR2_ipd, AR2, tipd_AR2);
        w_28 : VitalWireDelay (AL2_ipd, AL2, tipd_AL2);
        w_29 : VitalWireDelay (AR1_ipd, AR1, tipd_AR1);
        w_30 : VitalWireDelay (AL1_ipd, AL1, tipd_AL1);
        w_31 : VitalWireDelay (AR0_ipd, AR0, tipd_AR0);
        w_32 : VitalWireDelay (AL0_ipd, AL0, tipd_AL0);
        w_33 : VitalWireDelay (IOR7_ipd, IOR7, tipd_IOR7);
        w_34 : VitalWireDelay (IOR6_ipd, IOR6, tipd_IOR6);
        w_35 : VitalWireDelay (IOR5_ipd, IOR5, tipd_IOR5);
        w_36 : VitalWireDelay (IOR4_ipd, IOR4, tipd_IOR4);
        w_37 : VitalWireDelay (IOR3_ipd, IOR3, tipd_IOR3);
        w_38 : VitalWireDelay (IOR2_ipd, IOR2, tipd_IOR2);
        w_39 : VitalWireDelay (IOR1_ipd, IOR1, tipd_IOR1);
        w_40 : VitalWireDelay (IOR0_ipd, IOR0, tipd_IOR0);
        w_41 : VitalWireDelay (IOL7_ipd, IOL7, tipd_IOL7);
        w_42 : VitalWireDelay (IOL6_ipd, IOL6, tipd_IOL6);
        w_43 : VitalWireDelay (IOL5_ipd, IOL5, tipd_IOL5);
        w_44 : VitalWireDelay (IOL4_ipd, IOL4, tipd_IOL4);
        w_45 : VitalWireDelay (IOL3_ipd, IOL3, tipd_IOL3);
        w_46 : VitalWireDelay (IOL2_ipd, IOL2, tipd_IOL2);
        w_47 : VitalWireDelay (IOL1_ipd, IOL1, tipd_IOL1);
        w_48 : VitalWireDelay (IOL0_ipd, IOL0, tipd_IOL0);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK
    
        PORT (
            ALIn     : IN    std_logic_vector(HiAbit downto 0);
            ARIn     : IN    std_logic_vector(HiAbit downto 0);
            IOLIn    : IN    std_logic_vector(HiDbit downto 0);      
            IORIn    : IN    std_logic_vector(HiDbit downto 0);      
            IOLOut   : OUT   std_logic_vector(HiDbit downto 0);      
            IOROut   : OUT   std_logic_vector(HiDbit downto 0);      
            RWLIn    : IN    std_ulogic := 'U';
            RWRIn    : IN    std_ulogic := 'U';
            OELNegIn : IN    std_ulogic := 'U';
            OERNegIn : IN    std_ulogic := 'U';
            CELNegIn : IN    std_ulogic := 'U';
            CERNegIn : IN    std_ulogic := 'U';
            BUSYLNeg : OUT   std_ulogic := '1';
            BUSYRNeg : OUT   std_ulogic := '1';
            INTLNeg  : OUT   std_ulogic := '1';
            INTRNeg  : OUT   std_ulogic := '1'
        );
        PORT MAP (
            ALIn(0) =>  AL0_ipd,
            ALIn(1) =>  AL1_ipd,
            ALIn(2) =>  AL2_ipd,
            ALIn(3) =>  AL3_ipd,
            ALIn(4) =>  AL4_ipd,
            ALIn(5) =>  AL5_ipd,
            ALIn(6) =>  AL6_ipd,
            ALIn(7) =>  AL7_ipd,
            ALIn(8) =>  AL8_ipd,
            ALIn(9) =>  AL9_ipd,
            ARIn(0) =>  AR0_ipd,
            ARIn(1) =>  AR1_ipd,
            ARIn(2) =>  AR2_ipd,
            ARIn(3) =>  AR3_ipd,
            ARIn(4) =>  AR4_ipd,