k7r321882m.vhd

vhdl cod for ram.For sp3e

                    PeriodData      =>  TD_CNeg,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  (mode = c),
                    Violation       =>  Pviol_CNeg );

               VitalPeriodPulseCheck (
                    TestSignal      =>  KIn,
                    TestSignalName  =>  "K",
                    Period          =>  tperiod_K,
                    PulseWidthLow   =>  tpw_K_negedge,
                    PulseWidthHigh  =>  tpw_K_posedge,
                    PeriodData      =>  TD_K,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE,
                    Violation       =>  Pviol_K );

               VitalPeriodPulseCheck (
                    TestSignal      =>  KNegIn,
                    TestSignalName  =>  "KNeg",
                    Period          =>  tperiod_K,
                    PulseWidthLow   =>  tpw_K_negedge,
                    PulseWidthHigh  =>  tpw_K_posedge,
                    PeriodData      =>  TD_KNeg,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE,
                    Violation       =>  Pviol_KNeg );

               VitalInPhaseSkewCheck (
                    Signal1         =>  KIn,
                    Signal2         =>  CIn,
                    SkewS1S2RiseRise => tskew_K_C,
                    SkewData        =>  SD_K_C,
                    CheckEnabled    =>  (mode = c),
                    Trigger         =>  KCTRIG,
                    Violation       =>  Sviol_K_C );

               VitalInPhaseSkewCheck (
                    Signal1         =>  KNegIn,
                    Signal2         =>  CNegIn,
                    SkewS1S2RiseRise => tskew_K_C,
                    SkewData        =>  SD_KNeg_CNeg,
                    CheckEnabled    =>  (mode = c),
                    Trigger         =>  KCTRIGN,
                    Violation       =>  Sviol_KNeg_CNeg );

               VitalOutPhaseSkewCheck (
                    Signal1         =>  KIn,
                    Signal2         =>  KNegIn,
                    SkewS1S2RiseFall => tskew_K_KNeg,
                    SkewS2S1RiseFall => tskew_KNeg_K,
                    SkewData        =>  SD_K_KNeg,
                    CheckEnabled    =>  TRUE,
                    Trigger         =>  KTRIG,
                    Violation       =>  Sviol_K_KNeg );

               VitalOutPhaseSkewCheck (
                    Signal1         =>  CIn,
                    Signal2         =>  CNegIn,
                    SkewS1S2RiseFall => tskew_K_KNeg,
                    SkewS2S1RiseFall => tskew_KNeg_K,
                    SkewData        =>  SD_C_CNeg,
                    CheckEnabled    =>  (mode = c),
                    Trigger         =>  CTRIG,
                    Violation       =>  Sviol_C_CNeg );

                Violation := Tviol_A0_K OR Tviol_A0_KNeg OR Tviol_D0_K OR
                             Tviol_D1_K OR Tviol_D0_KNeg OR Tviol_D1_KNeg OR
                             Tviol_RNeg_K OR Tviol_WNeg_K OR Tviol_BW0Neg_K OR
                             Tviol_BW1Neg_K OR Tviol_BW0Neg_KNeg OR
                             Tviol_BW1Neg_KNeg OR Pviol_C OR Pviol_CNeg OR
                             Pviol_K OR Pviol_KNeg  OR
                             Sviol_KNeg_CNeg OR Sviol_K_C OR
                             Sviol_K_KNeg OR Sviol_C_CNeg;

            END IF; -- Timing Check Section

        --------------------------------------------------------------------
        -- Functional Section
        --------------------------------------------------------------------
        IF NOW < 10 ns  THEN
--            assert false report " start" severity note;
            IF To_UX01(CIn) = '1' AND To_UX01(CNegIn) = '1' THEN
                mode <= k;
            ELSE
                mode <= c;
            END IF;
            rdop:= false;
            wrop:= false;
        END IF;

        IF rising_edge(KIn) THEN
            IF WNeg_nwv = '0' THEN
                wrop := true;
                ASSERT (not(Is_X(BW0Neg_nwv)))
                    REPORT InstancePath & partID & ": Unusable value for BW0Neg"
                    SEVERITY SeverityMode;
                ASSERT (not(Is_X(BW1Neg_nwv)))
                    REPORT InstancePath & partID & ": Unusable value for BW1Neg"
                    SEVERITY SeverityMode;
                BW0Neg_reg := BW0Neg_nwv;
                BW1Neg_reg := BW1Neg_nwv;
                dat0_reg := Dat0In;
                dat1_reg := Dat1In;
            END IF;
            IF RNeg_nwv = '0' THEN
                rdop := true;
                raddr := To_Nat(AddressIn);
            END IF;
        END IF;

        IF rising_edge(KNegIn) THEN
            IF wrop = true THEN
                waddr := To_Nat(AddressIn);
                wrop := false;
                IF BW0Neg_reg = '0' THEN
                    IF Violation = '0' THEN
                        MemData0A(waddr) := To_Nat(dat0_reg);
                    ELSE
                        MemData0A(waddr) := -1;
                    END IF;
                END IF;
                IF BW0Neg_nwv = '0' THEN
                    IF Violation = '0' THEN
                        MemData0B(waddr) := To_Nat(Dat0In);
                    ELSE
                        MemData0B(waddr) := -1;
                    END IF;
                END IF;
                IF BW1Neg_reg = '0' THEN
                    IF Violation = '0' THEN
                        MemData1A(waddr) := To_Nat(dat1_reg);
                    ELSE
                        MemData1A(waddr) := -1;
                    END IF;
                END IF;
                IF BW1Neg_nwv = '0' THEN
                    IF Violation = '0' THEN
                        MemData1B(waddr) := To_Nat(Dat1In);
                    ELSE
                        MemData1B(waddr) := -1;
                    END IF;
                END IF;
            END IF;
        END IF;
        IF rising_edge(CNegInt) THEN

            dout_regA:=dout_tmpA;
            dout_regB:=dout_tmpB;

            IF rdop = true THEN
                rdop := false;

                datatmp := MemData0A(raddr);
                IF datatmp = -2 THEN
                    dout_tmpA(8 downto 0) := (others => 'U');
                ELSIF datatmp = -1 THEN
                    dout_tmpA(8 downto 0) := (others => 'X');
                ELSE
                    dout_tmpA(8 downto 0) := To_slv(datatmp, 9);
                END IF;

                datatmp := MemData1A(raddr);
                IF datatmp = -2 THEN
                    dout_tmpA(17 downto 9) := (others => 'U');
                ELSIF datatmp = -1 THEN
                    dout_tmpA(17 downto 9) := (others => 'X');
                ELSE
                    dout_tmpA(17 downto 9) := To_slv(datatmp, 9);
                END IF;

                datatmp := MemData0B(raddr);
                IF datatmp = -2 THEN
                    dout_tmpB(8 downto 0) := (others => 'U');
                ELSIF datatmp = -1 THEN
                    dout_tmpB(8 downto 0) := (others => 'X');
                ELSE
                    dout_tmpB(8 downto 0) := To_slv(datatmp, 9);
                END IF;

                datatmp := MemData1B(raddr);
                IF datatmp = -2 THEN
                    dout_tmpB(17 downto 9) := (others => 'U');
                ELSIF datatmp = -1 THEN
                    dout_tmpB(17 downto 9) := (others => 'X');
                ELSE
                    dout_tmpB(17 downto 9) := To_slv(datatmp, 9);
                END IF;

            ELSE
                dout_tmpA := (others => 'Z');
                dout_tmpB := (others => 'Z');
            END IF;
        END IF;

        IF rising_edge(CNegInt) THEN
            Q_zd <= dout_regA;
            CQNeg_zd := '1';
        END IF;

        IF rising_edge(CInt) THEN
            Q_zd <= dout_regB;
            CQ_zd := '1';
        END IF;

        IF falling_edge(CInt) THEN
            CQ_zd := '0';
        END IF;

        IF falling_edge(CNegInt) THEN
            CQNeg_zd := '0';
        END IF;
       --------------------------------------------------------------------
       -- File Read Section
       --------------------------------------------------------------------
       --  /       - comment
       --  @aaaaa  - <aaaaa> stands for address of a 36-bit word
       --  ddd ddd  - <ddd ddd> are bytes to be written
       --  data lines must be in pairs
       --            (aaaaa is incremented at every load)
       --  only first 1-7 columns are loaded. NO empty lines !
       --------------------------------------------------------------------
       IF NOW < 1 ns and (mem_file_name /= "none") THEN
           ind := 0;
           for i IN  0 TO TotalLOC LOOP
               MemData0B(i) := -2;
               MemData1B(i) := -2;
               MemData0A(i) := -2;
               MemData1A(i) := -2;
           END LOOP;
           WHILE (not ENDFILE (mem_file)) LOOP
              READLINE (mem_file, buf);
               IF buf(1) = '/' THEN
                   NEXT;
               ELSIF buf(1) = '@' THEN
                   ind := h(buf(2 to 6));
               ELSE
                   -- all bytes have the same value
                   MemData1A(ind) := h(buf(1 to 3));
                   MemData0A(ind) := h(buf(5 to 7));
                   READLINE (mem_file, buf);
                   MemData1B(ind) := h(buf(1 to 3));
                   MemData0B(ind) := h(buf(5 to 7));
                   ind := ind + 1;
               END IF;
           END LOOP;
       END IF;

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       =>  CQOut,
            OutSignalName   =>  "CQ",
            OutTemp         =>  CQ_zd,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => CInt'LAST_EVENT,
                      PathDelay         => tpd_C_CQ,
                      PathCondition     => TRUE ) ),
            GlitchData      => CQ_GlitchData );

        VitalPathDelay01Z (
            OutSignal       =>  CQNegOut,
            OutSignalName   =>  "CQNeg",
            OutTemp         =>  CQNeg_zd,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => CNegInt'LAST_EVENT,
                      PathDelay         => tpd_C_CQ,
                      PathCondition     => TRUE ) ),
            GlitchData      => CQNeg_GlitchData );

    END PROCESS;

        ------------------------------------------------------------------------
        -- Path Delay Processes generated as a function of data width
        ------------------------------------------------------------------------
        DataOut_Width : FOR i IN 17 DOWNTO 0 GENERATE
            DataOut_Delay : PROCESS (Q_zd(i))
                VARIABLE Q_GlitchData:VitalGlitchDataArrayType(35 Downto 0);
            BEGIN
                VitalPathDelay01Z (
                    OutSignal       => DataOut(i),
                    OutSignalName   => "Q",
                    OutTemp         => Q_zd(i),
                    Mode            => OnEvent,
                    GlitchData      => Q_GlitchData(i),
                    Paths           => (
                        0 => (InputChangeTime => CInt'LAST_EVENT,
                              PathDelay       => tpd_C_Q0,
                              PathCondition   => TRUE),
                        1 => (InputChangeTime => CNegInt'LAST_EVENT,
                              PathDelay       => tpd_C_Q0,
                              PathCondition   => TRUE)
                    )
                );

            END PROCESS;
        END GENERATE;
    END BLOCK;
END vhdl_behavioral;