idt71321.vhd

vhdl cod for ram.For sp3e

            IOLIn        : IN    std_logic_vector(HiDbit downto 0);
            IORIn        : IN    std_logic_vector(HiDbit downto 0);
            IOLOut       : OUT   std_logic_vector(HiDbit downto 0);
            IOROut       : OUT   std_logic_vector(HiDbit downto 0);
            OERNeg       : IN    std_ulogic := 'U';
            OELNeg       : IN    std_ulogic := 'U';
            RWR          : IN    std_ulogic := 'U';
            RWL          : IN    std_ulogic := 'U';
            CERNeg       : IN    std_ulogic := 'U';
            CELNeg       : IN    std_ulogic := 'U';
            BUSYLNeg     : OUT   std_ulogic := 'U';
            BUSYRNeg     : OUT   std_ulogic := 'U';
            INTLNeg      : OUT   std_ulogic := 'U';
            INTRNeg      : OUT   std_ulogic := 'U'
        );
        PORT MAP (
            ALIn(0) =>  AL0_ipd,
            ALIn(1) =>  AL1_ipd,
            ALIn(2) =>  AL2_ipd,
            ALIn(3) =>  AL3_ipd,
            ALIn(4) =>  AL4_ipd,
            ALIn(5) =>  AL5_ipd,
            ALIn(6) =>  AL6_ipd,
            ALIn(7) =>  AL7_ipd,
            ALIn(8) =>  AL8_ipd,
            ALIn(9) =>  AL9_ipd,
            ALIn(10) => AL10_ipd,
            ARIn(0) =>  AR0_ipd,
            ARIn(1) =>  AR1_ipd,
            ARIn(2) =>  AR2_ipd,
            ARIn(3) =>  AR3_ipd,
            ARIn(4) =>  AR4_ipd,
            ARIn(5) =>  AR5_ipd,
            ARIn(6) =>  AR6_ipd,
            ARIn(7) =>  AR7_ipd,
            ARIn(8) =>  AR8_ipd,
            ARIn(9) =>  AR9_ipd,
            ARIn(10) => AR10_ipd,
            IOLIn(0) => IOL0_ipd,
            IOLIn(1) => IOL1_ipd,
            IOLIn(2) => IOL2_ipd,
            IOLIn(3) => IOL3_ipd,
            IOLIn(4) => IOL4_ipd,
            IOLIn(5) => IOL5_ipd,
            IOLIn(6) => IOL6_ipd,
            IOLIn(7) => IOL7_ipd,
            IORIn(0) => IOR0_ipd,
            IORIn(1) => IOR1_ipd,
            IORIn(2) => IOR2_ipd,
            IORIn(3) => IOR3_ipd,
            IORIn(4) => IOR4_ipd,
            IORIn(5) => IOR5_ipd,
            IORIn(6) => IOR6_ipd,
            IORIn(7) => IOR7_ipd,
            IOROut(0) => IOR0,
            IOROut(1) => IOR1,
            IOROut(2) => IOR2,
            IOROut(3) => IOR3,
            IOROut(4) => IOR4,
            IOROut(5) => IOR5,
            IOROut(6) => IOR6,
            IOROut(7) => IOR7,
            IOLOut(0) => IOL0,
            IOLOut(1) => IOL1,
            IOLOut(2) => IOL2,
            IOLOut(3) => IOL3,
            IOLOut(4) => IOL4,
            IOLOut(5) => IOL5,
            IOLOut(6) => IOL6,
            IOLOut(7) => IOL7,
            OELNeg    => OELNeg_ipd,
            OERNeg    => OERNeg_ipd,
            RWL       => RWL_ipd,
            RWR       => RWR_ipd,
            CELNeg    => CELNeg_ipd,
            CERNeg    => CERNeg_ipd,
            BUSYLNeg  => BUSYLNeg,
            BUSYRNeg  => BUSYRNeg,
            INTLNeg   => INTLNeg,
            INTRNeg   => INTRNeg
        );

        SIGNAL IOL_zd  : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL IOR_zd  : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL IOL_pass: std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL IOR_pass: std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL BUSYLNeg_zd  : std_logic := '1';
        SIGNAL BUSYRNeg_zd  : std_logic := '1';
        SIGNAL BUSYLNeg_t   : std_logic := '1';
        SIGNAL BUSYRNeg_t   : std_logic := '1';
        SIGNAL INTLNeg_zd   : std_logic := '1';
        SIGNAL INTRNeg_zd   : std_logic := '1';
        SIGNAL INTLNeg_t    : std_logic := '1';
        SIGNAL INTRNeg_t    : std_logic := '1';
        SIGNAL RRead        : std_logic := '0';
        SIGNAL LRead        : std_logic := '0';
        SIGNAL RWrite       : std_logic := '0';
        SIGNAL LWrite       : std_logic := '0';
        SIGNAL SetIntR      : std_logic := '0';
        SIGNAL SetIntL      : std_logic := '0';
        SIGNAL ClearIntR    : std_logic := '0';
        SIGNAL ClearIntL    : std_logic := '0';
        SIGNAL reinvoke     : std_logic := '0';
        SIGNAL ALIn_t       : std_logic_vector(HiAbit DOWNTO 0);
        SIGNAL ARIn_t       : std_logic_vector(HiAbit DOWNTO 0);
        SIGNAL IOLIn_t      : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL IORIn_t      : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL ToggleWR     : BOOLEAN := FALSE;
        SIGNAL ToggleWL     : BOOLEAN := FALSE;
        -- Memory array declaration
        TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
                         RANGE  0 TO MaxData;
        SHARED VARIABLE MemData     : MemStore := (OTHERS => 0);

        SIGNAL Viol                : X01 := '0';

        -- tpd enable variable
        SHARED VARIABLE tpd_CER    : BOOLEAN := FALSE;
        SHARED VARIABLE tpd_OER    : BOOLEAN := FALSE;
        SHARED VARIABLE tpd_CEL    : BOOLEAN := FALSE;
        SHARED VARIABLE tpd_OEL    : BOOLEAN := FALSE;
    BEGIN
        --------------------------------------------------------------------
        -- Timing Check Section
        --------------------------------------------------------------------
        VITALTimingCheck: PROCESS(CELNeg, CERNeg, RWL, RWR, OELNeg, OERNeg,
                                 INTLNeg_t,INTRNeg_t, ALIn, ARIn, IOLIn, IORIn,
                                      BUSYLNeg_t, BUSYRNeg_t)
        --Setup/Hold checks variables
        VARIABLE Tviol_RWR_BUSYRNeg  : X01 := '0';
        VARIABLE Tviol_RWL_BUSYLNeg  : X01 := '0';
        VARIABLE Tviol_CERNeg_CELNeg : X01 := '0';
        VARIABLE Tviol_CELNeg_CERNeg : X01 := '0';
        VARIABLE Tviol_AL_AR0        : X01 := '0';
        VARIABLE Tviol_AL_AR1        : X01 := '0';
        VARIABLE Tviol_AL_AR2        : X01 := '0';
        VARIABLE Tviol_AL_AR3        : X01 := '0';
        VARIABLE Tviol_AL_AR4        : X01 := '0';
        VARIABLE Tviol_AL_AR5        : X01 := '0';
        VARIABLE Tviol_AL_AR6        : X01 := '0';
        VARIABLE Tviol_AL_AR7        : X01 := '0';
        VARIABLE Tviol_AL_AR8        : X01 := '0';
        VARIABLE Tviol_AL_AR9        : X01 := '0';
        VARIABLE Tviol_AL_AR10       : X01 := '0';
        VARIABLE Tviol_AR_AL0        : X01 := '0';
        VARIABLE Tviol_AR_AL1        : X01 := '0';
        VARIABLE Tviol_AR_AL2        : X01 := '0';
        VARIABLE Tviol_AR_AL3        : X01 := '0';
        VARIABLE Tviol_AR_AL4        : X01 := '0';
        VARIABLE Tviol_AR_AL5        : X01 := '0';
        VARIABLE Tviol_AR_AL6        : X01 := '0';
        VARIABLE Tviol_AR_AL7        : X01 := '0';
        VARIABLE Tviol_AR_AL8        : X01 := '0';
        VARIABLE Tviol_AR_AL9        : X01 := '0';
        VARIABLE Tviol_AR_AL10       : X01 := '0';
        VARIABLE Tviol_AL_OELNeg     : X01 := '0';
        VARIABLE Tviol_AR_OERNeg     : X01 := '0';
        VARIABLE Tviol_AR_RWR_s      : X01 := '0';
        VARIABLE Tviol_AL_RWL_s      : X01 := '0';
        VARIABLE Tviol_AL_CELNeg_s   : X01 := '0';
        VARIABLE Tviol_AR_CERNeg_s   : X01 := '0';
        VARIABLE Tviol_AL_CELNeg     : X01 := '0';
        VARIABLE Tviol_AR_CERNeg     : X01 := '0';
        VARIABLE Tviol_CELNeg_RWL    : X01 := '0';
        VARIABLE Tviol_CERNeg_RWR    : X01 := '0';
        VARIABLE Tviol_AL_RWL        : X01 := '0';
        VARIABLE Tviol_AR_RWR        : X01 := '0';
        VARIABLE Tviol_IOL0_CELNeg   : X01 := '0';
        VARIABLE Tviol_IOR_CERNeg    : X01 := '0';
        VARIABLE Tviol_IOL0_RWL      : X01 := '0';
        VARIABLE Tviol_IOR_RWR       : X01 := '0';

        VARIABLE TD_RWR_BUSYRNeg      : VitalTimingDataType;
        VARIABLE TD_RWL_BUSYLNeg      : VitalTimingDataType;
        VARIABLE TD_CERNeg_CELNeg     : VitalTimingDataType;
        VARIABLE TD_CELNeg_CERNeg     : VitalTimingDataType;
        VARIABLE TD_AL_AR0            : VitalTimingDataType;
        VARIABLE TD_AL_AR1            : VitalTimingDataType;
        VARIABLE TD_AL_AR2            : VitalTimingDataType;
        VARIABLE TD_AL_AR3            : VitalTimingDataType;
        VARIABLE TD_AL_AR4            : VitalTimingDataType;
        VARIABLE TD_AL_AR5            : VitalTimingDataType;
        VARIABLE TD_AL_AR6            : VitalTimingDataType;
        VARIABLE TD_AL_AR7            : VitalTimingDataType;
        VARIABLE TD_AL_AR8            : VitalTimingDataType;
        VARIABLE TD_AL_AR9            : VitalTimingDataType;
        VARIABLE TD_AL_AR10           : VitalTimingDataType;
        VARIABLE TD_AR_AL0            : VitalTimingDataType;
        VARIABLE TD_AR_AL1            : VitalTimingDataType;
        VARIABLE TD_AR_AL2            : VitalTimingDataType;
        VARIABLE TD_AR_AL3            : VitalTimingDataType;
        VARIABLE TD_AR_AL4            : VitalTimingDataType;
        VARIABLE TD_AR_AL5            : VitalTimingDataType;
        VARIABLE TD_AR_AL6            : VitalTimingDataType;
        VARIABLE TD_AR_AL7            : VitalTimingDataType;
        VARIABLE TD_AR_AL8            : VitalTimingDataType;
        VARIABLE TD_AR_AL9            : VitalTimingDataType;
        VARIABLE TD_AR_AL10           : VitalTimingDataType;
        VARIABLE TD_AL_OELNeg         : VitalTimingDataType;
        VARIABLE TD_AR_OERNeg         : VitalTimingDataType;
        VARIABLE TD_AR_RWR_s          : VitalTimingDataType;
        VARIABLE TD_AL_RWL_s          : VitalTimingDataType;
        VARIABLE TD_AL_CELNeg_s       : VitalTimingDataType;
        VARIABLE TD_AR_CERNeg_s       : VitalTimingDataType;
        VARIABLE TD_AL_CELNeg         : VitalTimingDataType;
        VARIABLE TD_AR_CERNeg         : VitalTimingDataType;
        VARIABLE TD_AL_RWL            : VitalTimingDataType;
        VARIABLE TD_AR_RWR            : VitalTimingDataType;
        VARIABLE TD_CELNeg_RWL        : VitalTimingDataType;
        VARIABLE TD_CERNeg_RWR        : VitalTimingDataType;
        VARIABLE TD_IOL0_CELNeg       : VitalTimingDataType;
        VARIABLE TD_IOR_CERNeg        : VitalTimingDataType;
        VARIABLE TD_IOL0_RWL          : VitalTimingDataType;
        VARIABLE TD_IOR_RWR           : VitalTimingDataType;

        -- Pulse width cheks variables
        VARIABLE Pviol_AL0    : X01 := '0';
        VARIABLE Pviol_AL1    : X01 := '0';
        VARIABLE Pviol_AL2    : X01 := '0';
        VARIABLE Pviol_AL3    : X01 := '0';
        VARIABLE Pviol_AL4    : X01 := '0';
        VARIABLE Pviol_AL5    : X01 := '0';
        VARIABLE Pviol_AL6    : X01 := '0';
        VARIABLE Pviol_AL7    : X01 := '0';
        VARIABLE Pviol_AL8    : X01 := '0';
        VARIABLE Pviol_AL9    : X01 := '0';
        VARIABLE Pviol_AL10   : X01 := '0';
        VARIABLE Pviol_AR0    : X01 := '0';
        VARIABLE Pviol_AR1    : X01 := '0';
        VARIABLE Pviol_AR2    : X01 := '0';
        VARIABLE Pviol_AR3    : X01 := '0';
        VARIABLE Pviol_AR4    : X01 := '0';
        VARIABLE Pviol_AR5    : X01 := '0';
        VARIABLE Pviol_AR6    : X01 := '0';
        VARIABLE Pviol_AR7    : X01 := '0';
        VARIABLE Pviol_AR8    : X01 := '0';
        VARIABLE Pviol_AR9    : X01 := '0';
        VARIABLE Pviol_AR10   : X01 := '0';
        VARIABLE Pviol_CELNeg : X01 := '0';
        VARIABLE Pviol_CERNeg : X01 := '0';
        VARIABLE Pviol_RWL    : X01 := '0';
        VARIABLE Pviol_RWR    : X01 := '0';

        VARIABLE PD_AL0       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AL1       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AL2       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AL3       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AL4       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AL5       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AL6       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AL7       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AL8       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AL9       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AL10      : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AR0       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AR1       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AR2       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AR3       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AR4       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AR5       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AR6       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AR7       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AR8       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AR9       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_AR10      : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_CELNeg    : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_CERNeg    : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_RWL       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE PD_RWR       : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Violation      : X01;
    BEGIN
        IF TimingChecksOn THEN
            -- Setup/Hold Checks
            Violation := '0';

        VitalSetupHoldCheck (
            TestSignal      => IOLIn,
            TestSignalName  => "IOL",
            RefSignal       => RWL,
            RefSignalName   => "RWL",
            SetupLow        => tsetup_IOL0_RWL,
            SetupHigh       => tsetup_IOL0_RWL,
            HoldLow         => thold_IOL0_RWL,
            HoldHigh        => thold_IOL0_RWL,
            CheckEnabled    => CELNeg = '0' AND OELNeg = '0',
            RefTransition   => '/',
            HeaderMsg       => InstancePath & partID,
            TimingData      => TD_IOL0_RWL,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_IOL0_RWL
            );

         VitalSetupHoldCheck (
            TestSignal      => IORIn,
            TestSignalName  => "IOR",
            RefSignal       => RWR,
            RefSignalName   => "RWR",
            SetupLow        => tsetup_IOL0_RWL,
            SetupHigh       => tsetup_IOL0_RWL,
            HoldLow         => thold_IOL0_RWL,
            HoldHigh        => thold_IOL0_RWL,
            CheckEnabled    => CERNeg = '0' AND OERNeg = '0',
            RefTransition   => '/',
            HeaderMsg       => InstancePath & partID,
            TimingData      => TD_IOR_RWR,